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Design Of Front-End Card And VME ReadOut Module For RPC Detector Of Daya Bay Neutrino Experiment

Posted on:2011-03-13Degree:DoctorType:Dissertation
Country:ChinaCandidate:H YangFull Text:PDF
GTID:1100360305966731Subject:Physical Electronics
Abstract/Summary:PDF Full Text Request
The Sino-American Daya Bay Reactor Neutrino Experiment aims at finding neutrinos with the solid angleθ13. The major part of the background comes from cosmic ray. And in order to separate these background noise from true events, water Cerenkov and RPC (Resistance Plat Chamber) detectors are adopted. In this article, the readout system of RPC detectors consisted by Front-End Cards (FEC),VME Readout Modules (ROM) and host computers is described in design techniques, functions and test results. The first part introduced the FEC and its FPGA firmware developments, including the baselines of system requirement, PCB design and logic functions together with tests and results. The following part mainly focuses on the VME Readout Module designs in detail, such as requirement, logic function design and self inspecting functions.Each module of RPC detector is consisted of 4 layers of readout strips, and each layer contains 8 RPC strips. That is,32 channels in total for one RPC module will be readout by one Front-End Card. The analog signal from those strips will be converted to digital format in FEC and labeled with relative time information if triggering standard is met. Local triggers are send from FEC to RPC Trigger Module(RTM) in VME crate and main trigger is feed back once the calculation result of trigger matrix in RTM is positive. Then after FEC receives main trigger, hit information will be send in serial code strings to the ROM via ReadOut Transceiver (ROT), which collects serial data strings from up to 15 FECs and encodes them into optical signals and transfers data to ROM.The RPC readout strips in the Daya Bay experiment is relatively wider and longer, resulting in the attenuation of signal amplitude. According to the baselines of system requirement of Daya Bay experiment, pulses over 30mV should be recognized as hits. Thus, FEC should be able to work well with 30mV threshold against possible noise and interferences. Also, running at 40M Hz system clock pace, the FEC must have no event data lost of all monitoring 32 channels while generating local trigger information for RTM. Once the main trigger is feedback, the FEC should be able to match the corresponding data with time stamp and send it in serial format.The ReadOut Module (ROM) in the VME crate collects optical data strings from up to 6 ROTs, that is,90 FECs in one experimental hall. Forcing the ROM to be able to decode and buffer all these amounts of serial data strings simultaneously before encoding them again into VME bus formats and pass them on to the system VME bus with absolute time stamp received from the GPS network. In order to avoid any possible lost of information, the ROM should have sufficient data buffers and precise timing controls. Also, the ROM is responsible for the configuration of FPGAs on FECs as well as providing system clock to ROTs and FECs. According to these requirements listed above, detailed introduction of both hardware and firmware design against noise and data lost would be given in this article, followed by corresponding tests of stability and reliability of FEC and ROM under given circumstances.As there is considerable similarity in the signal output of RPCs in DayaBay experiment and the RPCs in BESIII (Beijing Spectrometer),which is also a research project the authour has been envolved. We hope to build the DayaBay RPC readout system on the basis of successful design experiences in BESIII while improving and refining the design method to match the requirement of DayaBay Experiment.The major differences in RPC readout designs of these to research projects are:1. The DayaBay experiment has more strict requirements in higher accuracy and lower system noise level;2. The DayaBay RPCs are readout by modules while the BESIII RPCs are readout by layers. The DayaBay RPC module each has four layers, requiring the electronics readout system be capable of local-trigger functions to reduce noise in data.3. The structure of DayaBay RPC readout system is a star connection to reduce the chance of interference of ground planes while the BESIII system is readout by chains. Also, the DayaBay experiment adopted optical fibers for long distance data transferring.4. The DayaDay RPC readout system uses absolute time stamps for data synchronization.According to these differences, the article introduces the deisgn of DayaBay RPC readout systems in details.Some features in this design of the article:1. The RPC readout system uses a star-connection method to reduse ground noise; also, the data transimission from frontend to VME was via optical fiber, enhancing the anti-noise ability; the careful protection of high speed signals and rigorous segmentation of ground, assuring the anti-noise and anti-crosstalk abilities of FEC;2. The usage of local-trigger combined with system trigger in readout system enables the readout of Muons entering adjacent RPC modules.3. Adopting 12 bit DAC chips and a resistor network in threshold setting circuit to keep a high defination of readout; Enabling the self-inspecting and comparator checking function without analog switches via firmware techniques;4. Adding absolute time information to the data flow to align event data from defferent detector sub-systems;5. The adoption of up-to-date model of FPGA with large memory resources enables data buffering and stability under unusual situations;Among the above features, star connection and local-trigger method has not been found in previous RPC readout systems in China. Up to now, the design of FEC has passed the production review and the first batch of FECs are ready for installation and currently under observations in IHEP with RPC detectors. The ROM has passed final reviews and ready to be upgraded for production and joint debugging.
Keywords/Search Tags:Daya Bay Reactor Neutrino Experiment, RPC detector Readout System, FPGA, DAC
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