Base Three Architecture Storage Systems Related Issues

It is well known that multi-core processor is the mainstream of the next generation of computer architecture, and the chip multiprocessors (CMP) will be the dominant design paradigm of this area. In order to provide higher potential performance of multi-cores and realize bigger parallelism in programs, the programming model becomes the most important part of CMP design. Object-oriented paradigm (OOP) is based on the cognizance method of human being, the information hiding and data abstraction principles of OOP is the key of resolving complex problems and building parallel programming. Although, after several decades of development, it is widely accepted that OOP can improve code reusability and facilitate code maintenance, and software engineers and developers embrace object-oriented programming for benefits. However, the performance of object-oriented programs running on the non-object-oriented processors is always lower than procedure-oriented programs. As objects are independent of each other and have natural parallel essence, a multi-core processor supporting object-oriented computing not only alleviates the burden of parallel program design, but also can accelerate the execution of object-oriented programs. On the other hand, classical on-chip communication architecture uses a traditional Time-Division Multiplexed (TDM) bus. Bus-based architecture suffers from the clear bottleneck of the share media used for the transmission. Network on Chip (NoC), a new chip design paradigm, is expected to be an important architectural choice for CMP. Using network to replace global wiring has advantages of structure, performance and modularity. So a novel architecture which is based on the NoC and supports the object-oriented technology will become the major trend in the design of future generations of micro architectures. Researches in this dissertation were based on a novel object-oriented multi-core architecture named TriBA (Triplet-based Architecture). This dissertation was focused on the key aspects of memory architectures and object-oriented scheme. The main research works and contributions of this dissertation are listed as follows:(1) A novel Hierarchical Shared Memory Architecture (HSMA) which is suitable for TriBA architecture as well as its partially-inclusive memory mapping scheme was proposed. With the support of multi-ports shared storage, HSMA combined the distributed memory and shared memory to build a high efficiency memory system for TriBA. This work introduced the design and implement of HSMA, and the analysis of the structure shown that HSMA fully utilized the operation and communication localization of TriBA. HSMA has been proven to have superior arrangement, adaptability and flexibility. Besides, the partially-inclusive memory mapping scheme used on TriBA is very appropriate for object-oriented memory management.(2) Research on the support method and implement scheme for object-oriented paradigm in TriBA. TriBA as an object-oriented processor can achieve object properties and object operation in both software and hardware level. This work proposed an object supporting scheme including object mapping, object denotation, object realization and object management. Using object identifier as the reference of object, object indirect addressing achieved using multilevel object table. Object addressing space and address mapping process also explained.(3) Communication scheme design which was based on message passing for TriBA is proposed. Message passing was the only way of the communication among cores and objects in TriBA. First of all, the detailed format of the message, the definition of the message class and the message scheme were shown. Secondly, after comparing the topology properties of triplet-based network with 2D-Mesh interconnection, a novel strategy to provide high-performance communication for TriBA was introduce, which used the data channels along with the on-chip inter-core channels to transfer message and data. Thirdly, messages classified to six kinds according to the transaction mode. Simulation results shown that this strategy could enhance the efficiency of communication in TriBA.(4) A novel fair Dynamic Bandwidth Time Division Multiplex Access (DBTDMA) scheme for memory access scheduling was proposed. Since the gap between the speed of the processor and storage system, the performance of the whole processor is enslaved to the efficiency of the memory system. In object-oriented on-chip multi-core systems, the memory bandwidth is the key shared resource among cores, the memory access become the bottleneck of the performance. In order to improve the efficiency of the memory system, this work put forward a kind of scheme which made multi-cores sharing the memory bandwidth dynamically. Assistant with the alterable access priority of cores, DBTDMA can provide fairly memory access among cores and shorten the memory access latency.