Research On Key Technologies Of ATLAS STGC Front End Electronics Test

In 2012,the ATLAS/CMS experimental device on the LHC found Higgs boson,it marks the beginning of a new era in particle physics.The next step in the LHC experiment is to accurately determine the Higgs boson and its interaction with the ma-terial field to find new particles and new phenomena beyond the standard model.To achieve this physical goal,the LHC and its experiments will be carried out in Phase 1 and Phase 2 upgrades in 2018 and 2022,and the experimental detector system will be upgraded accordingly to ensure that high-energy,high-brightness proton collision-s environment to effectively collect data and carry out physical analysis.Because of the front-endelectronics system of sTGC consists of 1,536 FEBs with about322,000 readout of strips,wires and pads in total,in this paper,the front-end electronics testing technology is studied,and the 256-channel simulation test signal source and FEB con-figuration test board are designed based on the development requirements of ATLAS Phase 1 Muon NSW upgrade.In this paper,we first analyze the sTGC detectors front-end clcctronics testing requirements and test methods,and design a test signal source which simulates pulses originating from sTGC detector.We solve the problem of large-scale,multi-channel signal generation,and can provide different operating modes to test FEB function and performance.At present,it can provide six modes of 256-channel test signals,along with synchronous clock signal and pulse trigger signal,and it can form a complete test system with FEB.Second,aiming at the requirement of testing the new generation ASIC chips and its configuration system,the FEB configuration test board is developed.This research studies the configuration of the key chips on the FEB-VMM3 and TDS2,develops mul-tiple level standards and communication protocol,and verifies the whole data link.It provides technical reference for prototype FEB key chip configuration and data readout,as well as the final system configuration.Finally,the test platform is built on the basis of the two boards mentioned above,which provide a complete test scheme including the detector test signal source,front-end electronics readout,and system configuration.VMM2 chips on FEB has been tested,including channel gain test,threshold test,baseline test,and so on,the injection test can replace the detector to provide the trigger signal for FEB function verification.The FEB configuration test board realizes the operation and control of the SCA chip,including E-link,SPI,I2C,GPIO communication,implements the configuration of VMM3 and TDS2,while verifying the TDS2 4.8Gbps High-speed data transfer function.FEB con-figuration test board also conducted electronic integration test in CERN,it completed communication with Pad trigger and Router board.The innovation of the paper is as follows:1.Multi-channel,high-density,programmable test signal source is researched.The test method and test theory is completed,and multi-mode controllable 256-channel FEB board test signal generation function is implemented.A test platform has been designed to provide a fast and efficient test method for the production of FEB.2.Aiming at FEB key technology,we design a FEB configuration test board,and develop data communication protocols to realize the configuration of VMM3 and TDS2using GBT-SCA,and also verify the 4.8Gbps TDS data readout.The test results show that the technology can meet requirements of the future implementation of FEB.3.We research and implement the MAC layer network data transmission technolo-gy based on FPGA,which can implement high-speed network communication between computer and FPGA,the test result shows that the transfer rate can reach up to 926Mbps.