Research On Low Power ECG Algorithm And Memory Architecture

As the development of integrated circuit technology, many functional devices can be integrated on single chip. It is a great opportunity for the wireless sensor based wearable medical devices. Especially for the wearable electrocardiogram (ECG) devices, which can deliver ECG monitor and diagnosis at low cost in real time. Among the designing methodology, the microprocessor are widly used in the wearable ECG devices. However, the power consumption is still a big problem. This paper focus on the key techniques of designing an ultra low power processor for the wearable ECG device, and particularly study the method of ECG compression, ECG detection and designing of the low power memory architecture, there are some contributions in this paper:ECG compression based on sifting process of EMD. By studying the decomposition process of empircal mode decomposition (EMD), A new EMD based ECG compressor is presented. Utilizing the sifting process in EMD, the spline fitting function of the successive mean extrema together with the first intrinsic mode functions (IMFs) can perfectly reconstruct the ECG signal, the proposed method using the mean extrema for the compression. With optimal selection of the mean extrema and dead zone quantization, and the application of run length coding and Huffman coding for further compression, the experimental results regarding several records of the MIT-BIH arrhythmia database shows that the proposed methods can deliver better compression results and better recontronstruction results than the traditional EMD based compressors, and also have a better compression results than other recently developed transformation based ECG compressors. The compression algorithm can reduce the data amount of wireless transmission, and reduce the transmission power.A prejudgement based low power R-peak detection algorithm. By study the feature that most of the discrete wavelet transform (DWT) coefficient of ECG signal has low amplitude, a prejudgment based R peak detection algorithm are propsed. Based on the DWT based detection algorithm, a low computation complex QRS prejudging step is proposed for detection the suspect QRS waveform. Furthermore, and a RR interval prejudgment mechanism is employed to detecting the noise level of the ECG, and finally, use one decomposition scale or multiple decomposition scales to detect the R peak at different noise level. While keeping the detection accuracy, the algorithm reduces the DWT computation. Comparing to the DWT algorithm, the algorithm achieves 77.9% power reduction.Value locality based storage compression memory architecture for ECG sensor node. A value compression memory architecture for QRS detection in ultra-low-power ECG sensor nodes is proposed. Based on the exploration of value spatial locality in the most critical preprocessing stage of the ECG algorithm, a cost efficient compression strategy, which reorganizes several adjacent sample values into a base value with several displacements, is proposed. The displacements will be half or quarter scale quantifications; as a result, the storage size is reduced. The memory architecture saves memory space by storing compressed data with value spatial locality into a compressed memory section and by using a small, uncompressed memory section as backup to store the uncompressed data when a value spatial locality miss occurs. Furthermore, a low-power accession strategy is proposed to achieve low-power accession. An embodiment of the proposed memory architecture has been evaluated using the MIT/BIH database, the proposed memory architecture and a low-power accession strategy to achieve memory space savings of 32.5% and to achieve a 68.1% power reduction.Techniques proposed in this thesis facilitate the design of ultra low power processor design, especially for wearable ECG device, and have positive effects on both theoretical researches and practical applications.