| With the rapid development of communication technology and the Internet,the contradiction between the requirements of the network applications and the existing network service capabilities becomes more and more obvious.The ever-increasing network bandwidth,the richness and personalization of network services have placed higher requirements for switches and routers to build the Internet infrastructure.However,the function of network devices depends on the closed hardware,which makes it increasingly difficult to adapt to the various demands of new functions and new applications.Aiming at the above situation,Software-Defined Networking(SDN)proposed a new idea: decoupling the control plane and the data plane,so that the centralized control of the network can be realized through a unified controller.The network switching device only has the function of data forwarding and constitutes the data plane of SDN.Programmable interface is adopted between controller and switch to build dynamic,open and controllable network environment.Therefore,as an emerging network technology,SDN is receiving continuous attention in both academia and industry.The data plane is the infrastructure of SDN.It performs high-speed traffic processing and data forwarding according to the rules installed by the controller.The data plane directly affects the performance of the whole network.With the development of network bandwidth and the emergence of different new services,the SDN data plane needs to meet the requirements of high bandwidth,large capacity,more sophisticated flow classification and quality of service guarantees.This dissertation mainly focuses on the data plane of SDN.Starting from the functional structure of the data plane,combining with the requirements of practical engineering applications,this dissertation studies several key technologies and related problems of line-rate traffic processing in the data plane of SDN under high-bandwidth environment.The main contributions are as follows.1.The multiple flow table construction problem for SDN is studied.Aiming at the expansion of flow table scale and the inefficient storage resources utilization,a two-step multiple flow table construction algorithm is proposed.First,the match fields in the single flow table are split into multiple flow tables according to the flow classification vectors,so the wildcards in the flow table are eliminated.Second,the orthogonal decomposition is performed for each sub-tables,and the redundant entries are compressed.Simulation results show that this algorithm can compress more than 60% storage space of flow table and achieve a data throughput up to 100 Gbps.2.The high-speed packet classification problem in SDN data plane is studied.For the reason that existing methods cannot support range matching very well,this dissertation proposes a range supported bit vector(RSBV)packet classification algorithm and the bit vector for any types of fields(AFBV)packet classification algorithm.Firstly,in RSBV,the characteristic of range matching is analyzed,then the rules are pre-encoded and stored in memory.Secondly,the fields of an input packet header are used as addresses to read the memory,and the result of range matching is derived through pipelined Boolean operations.On this basis,the AFBV combines the RSBV and two-dimensional Stride BV,and the match fields are divided into different types and then processed in parallel.Therefore,the AFBV can support the packet classification for multi-dimensional fields efficiently,including exact matching,longest prefix matching,range matching and arbitrary wildcard matching.Through the two-dimensional pipelined hardware architecture,both of the proposed algorithms are able to achieve a high processing speed.Simulation results show that for a rule set of 512-bit width and 1K rules,the proposed AFBV algorithm can achieve a throughput of 520 million packet-per-second.Compared with the benchmarking methods,the proposed algorithm can support range matching efficiently,and the throughput is improved by 30%~44%,and the power consumption is reduced by 43% compared with TCAM solution.3.In the SDN data plane,the problem of high-performance queue management under the scenario of shared memory virtual output queueing is studied.This study can be divided into the following two parts.First,a shared-private queue management scheme(SPQM)is adopted to address the unfairness problem in shared-memory switching architecture under burst traffic.The key idea of SPQM is to divide the total memory space into shared area and private area.Each output port has a private memory area that cannot be used by other ports.The shared area is completely shared among all output ports.A theoretical queuing model of the proposed scheme is formulated and closed-form formulas are derived.By analyzing the numerical results,the nearly optimal partition of the switch buffer is obtained.Simulation results show that compared with the benchmarking methods,SPQM can reduce the overall blocking probability under non-uniform traffic.In addition,we have evaluated the performance of this method on the Ethernet switching platform based on FPGA,which proves that this method has the advantages of low time complexity and simplicity for hardware implementation.Second,under the scenario of multiple priority queueing,the Qo S optimization problem for multi-priority queues is studied.In order to achieve efficient utilization of the shared memory while providing different services for different priority queues,a backpressure-based Qo S optimization method(BQOM)is proposed.The key idea is to introduce a backpressure-based queue threshold control scheme.When the higher priority traffic is large,the lower priority traffic is suppressed,so that the higher priority traffic receives better service and the overall blocking probability can be reduced.A theoretical analysis is performed to examine the performance of the proposed scheme,and the optimal priority threshold setting is provided.Simulation results show that this method can reduce the overall blocking probability and increase the buffer utilization.Besides,the proposed method is implemented in FPGA platform and the performance of this method is further verified through a case study of an access network.Experimental results show that the proposed method works well in an actual access network.4.The problem of high-speed large-capacity packet buffer in SDN data plane is studied.Firstly,to address the requirements of both high-speed and large-capacity in SDN data plane,a parallel hybrid SRAM/DRAM architecture is designed.Besides,a dynamic memory allocation with hard timeout(DMA-HT)memory management algorithm is proposed to efficiently utilize the cache space and optimize the off-chip DRAM's bandwidth utilization.This algorithm dynamically allocates memory for each queue,and a timeout field is attached to each queue to control how long each queue stays in the SRAM.A queuing system is used to model the proposed algorithm,and multiple performance parameters are analyzed quantitatively.Through theoretical analysis,the optimal timeout can be obtained under a variety of traffic scenarios.Both simulations and FPGA implementations show that the proposed algorithm can and reduce packet loss rate and average delay significantly compared with previous solutions,and the DRAM's bandwidth utilization is improved by 2.1 times in the worst case. |
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