Design approaches for nanoscale circuits and architectures

CMOS silicon technologies are likely to run out of steam in the next 10-15 years despite revolutionary advances in the past few decades. Molecular and other nanoscale technologies show significant promise but it is unlikely that they will completely replace CMOS, at least in the near term. This dissertation explores opportunities for using CMOS and nanotechnology to enhance and complement one another in hybrid circuits. The first step in this work is the development and enhancement of a universal device model (UDM) used in circuit simulations. This model is used to analyze a nanoscale memory array designed using an approach considering the interface between CMOS and nanoelectronics. Options for signal restoration at the nanoscale are then considered and lead to the design of a novel programmable logic array (PLA) based on majority logic. It is believed that such systems will be able to sustain the historical advances in the semiconductor industry while addressing manufacturability, yield, power, cost and performance challenges.