Wireless neural recording and stimulation SoCs for monitoring and treatment of intractable epilepsy

This dissertation presents the system architecture and implementation of two wireless systems-on-chip (SoCs) for diagnostics and treatment of neurological disorders. It also validates the SoCs as an electronic implant for preoperative monitoring and treatment of intractable epilepsy.;The first prototype SoC is a neural recording interface intended for wireless monitoring of intractable epilepsy. The 0.13microm CMOS SoC has 64 recording channels, 64 programmable FIR filters and an integrated 915MHz FSK PLL-based wireless transmitter. Each channel contains a low-noise amplifier and a modified 8-bit SAR ADC that and can provide analog-digital multiplication by modifying the ADC sampling phase. It is used in conjunction with 12-bit digital adders and registers to implement 64 16-tap FIR filters with a minimal area and power overhead. In vivo measurement results from freely moving rodents demonstrate its utility in preoperative monitoring epileptic seizures.;Treatment of intractable epilepsy by responsive neurostimulation requires seizure detection capabilities. Next, a low-power VLSI processor architecture for early seizure detection is described. It the magnitude, phase and phase synchronization of two neural signals---all precursors of a seizure. The processor is utilized in an implantable responsive neural stimulator application. The architecture uses three CORDIC processing cores that require shift-and-add operations but no multiplication. The efficacy of the processor in epileptic seizure detection is validated on human EEG data and yields comparable performance to software-based algorithms.;The second prototype SoC is a closed-loop 64-channel neural stimulator that includes the aforementioned seizure detector processor and is used for preventive seizure abortion. It constitutes a neural vector analyzer that monitors the magnitude, phase and phase synchronization of neural signals to enable seizure detection. In a closed loop, abnormal phase synchrony triggers the programmable-waveform biphasic neural stimulator. To implement these functionalities, the 0.13microm CMOS SoC integrates 64 amplifiers with switched-capacitor (SC) bandpass filters, 64 MADCs, 64 16-tap FIR filters, a processor, 64 biphasic stimulators and a wireless transmitter. The SoC is validated in the detection and abortion of seizures in freely moving rodents on-line and in early seizure detection in humans off-line. The results demonstrate its utility in treatment of intractable epilepsy.