Non-Classical MOSFETs: Design, Modeling, and Characterization

Low power and high density requires scaling of MOSFETs in VLSI. As the Si based bulk MOSFETs scale down to the limit imposed by gate oxide tunneling induced gate leakage, short channel effects (SCEs) induced loss of control on electrostatic integrity, high body doping induced high Vt variation, and band-to-band tunneling induced high substrate leakage, etc., two categories of novel MOSFETs are being intensively investigated: Si multiple gate MOSFETs and high mobility III-V material based MOSFETs. Among all types of Si multiple gate MOSFETs, nanowire MOSFET is drawing quite a few attentions for its superior electrostatic control through all-around gate structure. High mobility III-V MOSFETs are considered as a principal candidate to achieve high speed without too aggressive scaling, which can keep good control of electrostatic integrity. This dissertation is primarily devoted to modeling and characterization of challenges and features which are becoming pronounced in aggressively scaled MOSFETs and high mobility material based MOSFETs. High-kappa dielectric on III-V MOS capacitors are intensively characterized and modeled with the focus on defects at insulator-semiconductor interface as well as inside the oxide, which are grand challenges for III-V MOSFETs. A distributed bulk-oxide trap model is developed to account for the commonly observed frequency dispersion of small signal capacitance-voltage and conductance-voltage data in accumulation and near flat band region. The observed C-V humps in depletion to strong inversion are modeled by interface states model. For III-V MOSFETs design, SCEs and raised source/drain issues are studied using TCAD simulation. Fabricated III-V MOSFETs are characterized and mobility is extracted through experimental current voltage data and multiple frequency gate to channel capacitance measurement and data. For multiple gate Si MOSFETs, this dissertation focuses on nanowire MOSFETs. SCEs based on generalized scale length theory are discussed and compact models are proposed and validated by TCAD simulation. Quantum confinement effects on Vt shift in nanowire MOSFETs with anisotropic effective mass are modeled. Scaling limit is projected for extremely scaled nanowire MOSFETs based on Vt shift sensitivity and scale length theory. Finally, inversion layer capacitance beyond the conventional bulk Si-based MOSFETs is investigated for III-V MOSFETs as well as two typical 3-D transistors, namely symmetric double-gate MOSFETs and nanowire MOSFETs.