| Device physics limitations of conventional complementary metal-oxide semiconductor (CMOS) transistors are likely to cause diminishing integrated circuit performance improvement in the sub 100-nm regime. At these dimensions, quantum effects become prominent leading to realization of devices utilizing quantum-mechanical tunneling transport mechanisms for obtaining picosecond device switching speeds. The negative differential-resistance (NDR) current-voltage (I-V) characteristic of such devices, achieved due to resonant tunneling, is also ideally suited for the design of compact self-latching logic circuits. While resonant tunneling devices have been demonstrated using III-V materials, their large absolute current values and low integration levels have limited their use to niche high-performance small-scale circuits. Given the advantages of resonant tunneling devices, it is attractive to envision compact, high-functionality NDR circuits implemented in a technology such as CMOS that offers low power dissipation and very high integration levels. Even as research in cointegration of resonant tunneling devices in Silicon, referred to as quantum MOS (QMOS), is ongoing, this dissertation presents novel combinational and bistable logic families, and compact flip-flop circuits using resonant tunneling diodes (RTDs) and MOS transistors. Analytical studies of static and dynamic QMOS performance parameters yield expressions for theoretical circuit comparison with CMOS, and also for optimizing RTD characteristics. QMOS circuits are characterized using SPICE simulation, and simulation-based comparison of QMOS and CMOS circuits highlights potential area-power-delay savings of this new circuit technique. The folded I-V characteristic of RTDs allows gate-level bistable-clocked-mode system operation. Performance improvement of such fine-grained QMOS pipelines arises from compactness of logic design, elimination of pipeline latch area, delay and power overhead, and high switching speed of the RTD. A pipelined carry-save multiplier and a 32-bit parallel correlator are designed to study the system-level advantages of QMOS logic. In particular, signal processing systems and communication systems benefit from fine-grained pipelining due to minimal data dependence and large volume of similar computations at each cycle. In the absence of a fabrication process that cointegrates RTDs in Silicon, a study of various QMOS prototyping schemes is presented that identifies the best means to verify system-level behavior of QMOS circuits while research in RTD-CMOS cointegration continues. |
