Hot-carrier reliability of CMOS integrated circuits

In MOS devices, channel carriers flow through a high field region and gain energy. These “hot” carriers can cause long term damage of the gate-oxide/Si interface, leading to degradation of the device characteristics and circuit performance. As devices are scaled to meet circuit density and speed specifications, hot-carrier reliability has been a great concern. This research aims to advance the understanding of several key aspects of the hot-carrier reliability of advanced CMOS devices and integrated circuits.; New technologies such as trench isolation can influence the hot-carrier reliability. Channel. width dependence of hot-carrier induced degradation in MOS devices with shallow trench isolation is investigated and enhanced degradation is observed in devices with narrow channel widths. The width dependence of the impact ionization rate fails to explain this effect. We propose that the mechanical stress resulting from the shallow trench isolation process is responsible for this enhanced degradation. An empirical model is developed to correlate the amount of enhanced degradation and the mechanical stress in the device.; The reliability and performance of NMOS asymmetric LDD devices (with no LDD on the source side) are compared with that of conventional LDD devices. At a fixed V_dd, asymmetric LDD devices exhibit higher I_dsat and shorter hot-carrier lifetime. To maintain the same hot-carrier lifetime, asymmetric LDD devices must operate at a lower V_dd, however higher I_dsat is obtained even at the lower V_dd. For the same hot-carrier lifetime, ring oscillators with asymmetric-LDD NMOS devices achieve 5% (10% if PMOS device also had asymmetric LDD) higher speed, and 10% lower power. Asymmetric LDD devices can improve circuit speed and power consumption without sacrificing reliability and are thus an interesting alternative for future high performance technologies.; Circuit hot-carrier reliability simulation based on SPICE circuit simulators is used to study the reliability of logic gates. Experimental data and simulation results are in good agreement when the simulation model is carefully calibrated based on available stress data. The calibrated reliability model can then be used to predict the hot-carrier reliability of any circuit structure. This study validates the nascent technology of reliability simulation.; Experimental verification of a novel rule-based hot-carrier reliability simulation methodology is performed. Long term hot-carrier stress on a 64-bit ripple-carry adder is carried out. Experimental results are compared with rule-based simulation results to demonstrate that rule-based simulation can predict hot-carrier induced speed degradation of CMOS digital circuits. Circuit designers can make use of fast rule-based simulation to quickly obtain feedback on circuit hot-carrier reliability.; The statistical variation of NMOS hot-carrier lifetime is studied. Devices close to one another have more similar lifetimes. Due to the statistical nature of device hot-carrier lifetime, hot-carrier induced circuit delay degradation in the critical paths is a statistical distribution rather than a deterministic parameter. A statistical hot-carrier simulator is developed to predict the impact of the statistical variation of device hot-carrier lifetime on circuit reliability.