Research On Random Number Generator And Hardware Circuit System Of Continuous Variable Quantum Key Distribution

With the development of information technology,the degree of social informatization has gradually increased.In the modern society,information security problems occur from time to time.Quantum Key Distribution(QKD),as the closest practical technology in quantum cryptography,can realize the theoretical unconditional security of both parties in communication,and has become one of the effective technical means to resist information security risks.Among them,Continuous Variable Quantum Key Distribution(CV-QKD)uses the orthogonal quantum states of the optical field as the information carrier,adopts standard communication devices and general detection technology,and can be integrated with the existing classical optical communication network.It has obvious advantages in terms of technical difficulty and implementation cost.At present,the development of this technology is becoming more and more mature,and it is gradually developing rapidly from experimental research to practical application.In the development of CV-QKD from proposing protocol to experimental realization,a number of key technologies have been derived,including true random number technology,high-speed synchronous clock recovery technology,real-time relative phase precision locking technology,real-time polarization dynamic locking technology,real-time data post-processing technology,dense wavelength division multiplexing technology and polarization multiplexing technology,etc.In order to meet the current performance requirements of CV-QKD in terms of practicality,many vital technologies still need to be further studied.In the Gaussian modulation-based coherent state protocol CV-QKD system studied in this paper,the quality of the random number directly determines the security of the system,and it plays an essential role in the CV-QKD system.Alice needs to modulate random Gaussian information onto the p-quadrature and q-quadrature to prepare a quantum state,while Bob needs to randomly select the measurement base.If these random information is obtained or tampered with by malicious attackers,then the CV-QKD process is essentially the same as the process of direct transmission through the public channel,and there is no security and confidentiality at all.On the other hand,the hardware circuit system is an important support for the CV-QKD system,and its indicators directly limit the overall performance of the CV-QKD system.For example,the main clock frequency of the hardware system directly determines the final system key rate,the high-precision acquisition of the detector signal can realize the accurate evaluation of the excess noise of the system,and the precise control of the high-speed real-time phase and polarization lock will improve the stability of the system.Therefore,the hardware circuit system and true random number generation technologies are the core components and key technologies of the system.When facing the high stability and high-performance requirements of the practical prototype system,there is an urgent need for further research.This thesis mainly focuses on the two key technologies of CV-QKD hardware circuit system and true random number generation,mainly including the following aspects:We have researched and implemented a high-speed classic true random number generator based on Field Programmable Gate Array(FPGA).We analyze the main factors that affect the security and randomness of the classic true random number generator.The phase jitter of the self-timed ring is selected as the source of entropy,and random numbers are extracted from the raw sequence with the Toeplitze extractor that has been theoretically proven safe.By modeling the entropy source and the sampling process,the lower limit of the min-entropy is calculated to ensure the randomness of the extracted random sequence.We analyzed the influence of the entropy source and key parameters in the post-processing on the throughput and consumption of hardware resources.Through the joint optimization of the entropy source channel parallelism in the random number generator structure and the extraction efficiency of the extractor,the FPGA XC7VX485T achieves a throughput of 10 Gbps with a total hardware resource consumption of 7.29%,which effectively improves the utilization of hardware resources.Our research has provided an optimized design strategy for the realization of a high-speed random number generator.We have researched and implemented a quantum random number generator based on boundary bins removal and parallel multi-intervals sampling.By analyzing the calculation process of the worst-case min-entropy and the average conditional min-entropy in the basic sampling model of the random generator,the main factors that affect the conditional min-entropy are determined.On this basis,two improved methods are proposed to enhance the randomness independent of classical noise in the worst-case scenario and the average scenario,and the main parameters in the Quantum Random Number Generator(QRNG)are optimized.By removing boundary saturation bins,the influence of the conditional probability of the boundary bins on the conditional min-entropy is suppressed,and the randomness of the output sequence is enhanced.By adopting a multi-channel parallel sampling method,the limited resolution of a single Analog-to-Digital Converter(ADC)is eliminated.At the same time,combined with the non-equal bins sampling method,the channel sampling input range is optimized to obtain more conditional min-entropy independent of classical noise.Finally,the above two methods are applied to QRNG based on quantum vacuum fluctuation.Experiments show that,compared with the basic model of_n(28)8(_n(28)16),the upper bounds of the conditional min-entropy of the joint model are approximately increased by 31.30%(19.62%).Under the same equivalent resolution,for n(28)8 and n(28)10,the joint model can still achieve 4.77%and5.71%improvements,respectively.We have designed and implemented the CV-QKD real-time hardware circuit system.By analyzing the functions and main performance of the CV-QKD system,a hardware circuit system based on FPGA is designed and implemented.It mainly includes three parts:high-speed data acquisition daughtercard,high-speed control system card,and real-time data post-processing card.The high-speed data acquisition daughter card realizes the functions of high-precision acquisition and signals output of the detection signal of the CV-QKD system;the high-speed control system card mainly realizes The real-time requirement in the GG02 protocol requires higher underlying protocol functions.The data real-time post-processing card specifically provides support for real-time information reconciliation and privacy amplification.By designing logic functions such as high-speed data acquisition,high-speed data buffering,and multi-channel data transmission,good coordination between the hardware circuit and the implementation of the protocol is realized.The test result of the hardware circuit system has reached the expected goal.The above work effectively solved the real-time processing capability and stability problems of the CV-QKD prototype system and promoted the practicality of the system.