Design Of High Precison Timekeeping Circuit And Its Realization On The Navigation Receiver

Satellite navigation positon system can not only apply to civil field service but also to military affairs,which has gigantic economic returns and social benefits.In satellite navigation positon system,the direct P code(precise distance measurement code)acquisition by receiver is the important content of GPS modernization plan, which is also the key technology of BD-2 satellite navigation system.Generally,the P code acqusition is realized under the guidance of C code(average distance measurement code)acqusition.C code has a shorter period,lower chipping rate,more easily distrubing and cheating enviroment by enemy than P code.It is difficult to acquire P code under the guidance of C code in the intensely disturbing and cheating environment.Therefore,the direct P code acquisition technology has importance to satellite navigation position system in modern abominable electronic warfare environment.And the key of the direct P code acqusition is to ascertain initiation acqusition moment,the more precise of initiation acqusition moment,the simpler of acqusition process,the shorter of acqusition time.Therefore,the timekeeping circuit which providing high-precision time criterion for P code acqusiton is playing important role in P code acqusiton.Firstly the timekeeping technology and direct sequence spread spectrum technology are analysed,then the BD satellite navigation system and navigation receiver are detailedly introduced.Secondly the high-accuracy timekeeping circuit composed of the real time clock module,frequency criterion module and power management module is designed.Thirdly the principle of P code acqusiton and its design scheme are analysed.Based on the EDA and navigation technology,one kind of high-accuracy time keeping circuit for direct P code acqusiton applying to BD navigation receiver is developed.The main research content of this thesis include the followings:(1)According to system design requirements,studying and analysing with the systematic performance index,this thesis establishes the scheme of timekeeping circuit,selects proper component,and analyses the frequency criterion index as the basis of timekeeping circuit.(2)The thought of modularization and synchronization are used to design the real time clock module in time keeping circuit owing to VerilogHDL,and accomplishes simulation,makes it being able to keep free sequence when programming CPLD device.(3)The direct P code acqusiton scheme is introduced,and the read-write interface between the DSP processor and the timekeeping circuit in FPGA is designed, which is to realize the timekeeping circuit communicaiton with other function module, the whole realizing result of software code is achieved in this thesis.(4)The system main performance parameter in experiment's foundation is given and analysed.