The Analysis And Design Of Radiation-Hardened CMOS Integrated Circuits

In this paper, a 10k-gate radiation tolerant CMOS gate array has been developed to assess the intrinsic radiation hardness of circuits built at standard commercial CMOS foundries. In this study, the design procedures for mitigating radiation effects mechanisms have been implemented in a gate array design, we have obtained samples of integrated circuits test structures manufactured by Wuxi CSMC-HJ using their 0.6- m CMOS process. We have demonstrated that the integrated circuit test structures fabricated at standard commercial foundries can be radiation tolerant at total does greater than 100krad(Si).The radiation environment of outer space is capable of effecting CMOS devices in three ways. The first, termed total does, is accumulated ionizing radiation effects. Two other effects are transient phenomenon called Single Event Upset (SEU) and Single Event Latchup (SEL). In this paper, some means to harden the devices against these phenomena are used. Guard banding around NMOS and PMOS transistors greatly reduces the susceptibility of CMOS circuits to lachup. The use of edgeless NMOS transistors in place of 2-edgeless transistors eliminates the excessive radiation-induced edge leakage in many CMOS parts after irradiation. And finally, the use of redundant latches minimizes single-event upset (SEU) rates in commercial latches.In order to evaluate radiation hardness for the newly developed 10k-gate CMOS gate array, the samples of integrated circuits test structure have been designed. The irradiation wasperformed at room temperature, using a 60Co source with a does rate of 16.4 rad(Si)/sec up to 100krad(Si). The samples were bias at 5V for dynamic operation during irradiation. The test results of post-radiation indicated that no samples were failed functionally and all samples' DC parameter, such as high-level output voltage (VOH), low-level output voltage (VOL), high-level input voltage (VIH), low-level input voltage (VJL), input current (Im) and quiescent supply current (IDD), matched the specified limit.