Research And Implementation Of Structure Of Programmable Logic Device(CPLD/FPGA)

Programmable logic device(CPLD/FPGA) has been applied in many fields , including industry automatization, communication, Aviation and aircraft, vehicle electronics, medicine, consume electronics and other high technology fields. The advantages include simple programming method, high speed, high reliablitity, short research cycle, standard design language and tools of exploitation, strong function, wide application, super flexibility, easy to study, making it playing more and more important roles in market.Various all kinds of programmable principles, the logic architecture and interconnect resource of CPLD/FPGA have been described first, following by the In -System-Program technology and design flow of PLD in this thesis. Besides, some key parameters of the CPLD/FPGA structure have been analyzed and discussed in order to get the best values. For example, the width, spacing distance and length of wires have great influence on the area,delay and power.The optimal values respective to the detailed library are obtained. Second,the array sensitivity amplifier has been discussed and optimized. Although the layout area increases ,the performance is inproved without additional increase in power. Finally, When reading two adders designs via FPGA, the Altera Quartus II software is applied to analyze and compare their performance ,areas and power consumption between the combinational and self-timed adders.