Study And Design Of A High-Speed Viterbi Decoder

Viterbi algorithm is the most likelihood decode algorithm of convolutional code. Viterbi decoder means the hardware implementation of Viterbi algorithm. In the area of communication, convolution code is very popular, so how to improve the decoding throughput to be applied to different digital communication systems that need high throughput is important.A high-speed (2, 1, 6) Viterbi decoder is presented in this paper. The Branch Metric Unit adopt 3-bit quantization soft decision to obtain 2～3dB gain. In this design architecture of Add-Compare-Select unit in Viterbi arithmetic is improved, which is based on parallel Radix-4 architecture and bit-level Carry-Save Arithmetic, the carry chain of traditional Ripple-Carry Adder is eliminated. Therefore, the critical path of Viterbi decoder is shortened; decoding delay is reduced. The design of Survivor path Memory Unit adopts Register-Exchange output pattern.In this paper, the Top-Down Design Method is adopted in the designed Viterbi decoder, using Verilog hardware description language for the description of the RTL level, and conducted a joint simulation using ActiveHDL7.2 and Simulink in the AWGN channel, measured BER performance achieve the requirement of the project standard. After using Synplifypro8.1 to synthesis and the decoder critical path analysis, a high throughput is achieved. The proposed Viterbi decoder has great chance to be applied to different digital communication systems that need high throughput.