The Research Of Serial ATA Protocol And Its FPGA Implementation

The Parallel ATA Protocol has already been used on disk interface for the past twenty years. Nowadays the protocol's drawback limits the system's performance, and will be replaced by the Serial ATA (SATA). As a high speedy serial bus, SATA includes the point to point transfer mode, embedded data and commands checking unit, support hot plug. The band width is 150MB per second (SATA version 1.0a) or 300MB per second (SATA version 2.0). The products based on SATA are used greatly now, most of which are provided by the other countries. And no SATA IP CORE for FPGA is developed independently in china. So it's significant to design a SATA IP CORE.This paper firstly analyzes the SATA protocol, and develops the layer model of SATA adapter. The layer model contains application layer, transport layer, link layer and physical layer. To accomplish the IP CORE, it introduces the design language, design tools and selected chip. And it explained the whole IP CORE in detail, which includes all the modules separately. At last, it finished all the steps including codec, synthesis and test.The thesis designs the 1.5Gbps differential serial signal communication channel based on RocketIO MGT. And it accomplishes multiple state machine cooperation design using parallel structure. To improve the speed, it utilizes the pipeline and design parallel in high speedy design. Considering the fact that different parts have different complexity, the design uses different pipelines. By Chipscope pro and SATA bus analyzers, the debugging process become faster and more accurate. It achieves the SATA IP CORE based on the SATA 1.0a protocol.Finally the test data indicates that the design fulfills the protocol's requirements. The SATA IP CORE is highly integrated and low cost. It enables the development of solid-state disk more convenient.