Research And Implementation Of High Reliability Low Power SRAM For X Microprocessor

With the rapid development of microelectronics technology, all kinds of memory are embedded in SOC to improve its performance, especially the SRAM. Embedded SRAM is preferred for design of embedded memory because of being compatible with standard CMOS techlogy. The area and power of Memory cell array of SRAM account a large proportion of a chip's, so the performance and power of SRAM play a decisive role of the whole embedded system's. This shows that it is very important to design SRAM of high performance, low power, small size and high reliability in SOC. It is the best programme to design this SRAM based on demand of SOC and evaluation of performace parameters.In this paper, a high reliability and low power 0.25μm CMOS SRAM which is 56k(512×16bit) and works on 100MHZ is designed using full custom design method. The area of Single SRAM is 4.78mm~2. The access time of data is 1.38ns. The largest power of access is 96.49mw. Some methods such as divided word line/multilevel bit-line, multilevel static CMOS decoding and self-timed are adopted to make the power more than 25% lower than the normal. Abundant design is used to make the performance of SRAM achieve the military standard (-55℃—125℃, VDD±10%, aseismatic etc.). Further, the array redundancy design improves the yield of SRAM products greatly. Simulation and test shows that its performance meets design requirements. It is fabricated successfully finally.