A Design Of Standard Cell Library Functional Test Module

This paper designed a standard cell library functional test module to achieve 0.35um standard cell library physical verification and ensure every standard cell in this set of library have a good manufacturability and the correctness of logic function. The design can also shorten the cell library verification cycle while improving the quality of cell libraries.In this paper, it poses a comprehensive analyse on the standard cell library functional test module requirements and propose a design plan. It focuses on how to use reference flow to achieve the design from the standard cell library functional test module RTL-level Verilog model to the final proven layout and using Perl scripts to generate test pattern. Finally using Maverick testing system to load test pattern and verify the module. In the process, use Design Compiler to synthesis design. Use IC Compiler to do clock tree synthesis, place and route. Use Prime Time to do static timing analysis. Use Formality to the post-layout netlist for formal verification. Use VCS to do dynamic timing simulation with interconnect delay. Base on the input and output ports level conditions that recorded during the simulation, use Perl script to generate the final test pattern. Finally, test chip functional test module is able to pass the test pattern that not only prove the design is right, but also to verify the 0.35-micron standard cell library standard cells'logic function are correct.