The Design And Implementation Of HDLC Frame Transceiver Based On The FPGA Technology

ABSTRACT:HDLC, which is widely applied to control protocol of Data Link Layer, is based on bit. With the purpose to implement the funtion of frame transmission under HDLC procedure, this design proposed a frame transceiver based on further analyze and research on the frame structure under HDLC procedures and protocol, by means of FPGA platform, which belonged to the project "Localization of Guangzhou Metro Line No.1"The design achieved implementations of the funtion of flag gneration and detection, zero insertion and deletion, FCS generation and verification accordingly by discussing the method of sub-functional implementation of HDLC frame transceiver, which were implemented inside the FPGA. The sub-functions of the HDLC frame transceiver were connected and controlled by means of adding register configuration and compel Zero funtion of state transmission-default mode.The design, which were implemented the sub-functional and the whole functional block inside the FPGA, was written with both VHDL and Verilog HDL, and pre-simulated, pin-assigned, synthesized based on Quartus 118.0, finally the post simulation is carried out by Modelsim6.1+Altera platform. The design had downloaded to Cyclone-the development board by means of JTAG mode after simulating test. It was concluded that the design were tested correctly and post-simulated under HDLC functional protocols, frame structure and the funtion of FCS verification.After finishing the design of HDLC frame transceiver, with the purpose of ensuring its reliability and high efficiency of communication, the thesis had carried out control and analysis by means of state machines'transmission, focusing the feature of frame stream clock frequency. Finally the boundary of clock communication had been concluded, which means the communication rate had been improved notably on the basis of ensuring its reliability. To conclude, the thesis is crucial to the relative localization of vehicle bus.