Design Of The Data Transmitter For 3.125G High-speed Serial RapidIO Interface

As the world's first and only international standard for embedded systems interconnect, RapidIO is system-level interconnect technology mainly used in high-performance DSP system and embedded system. RapidIO protocol is implemented all by hardware instead of software. So compared with other interconnect technology, RapidIO has great advantages in aspects of transmission rate, routing, switching, fault-tolerant error correction, and easy using. Based on RapidIO interface has the features of high-speed and high reliability, the data transmitter of RapidIO is implemented through full-custom design. In this paper, the work and contribution is in the following aspects:1. We analyze high-speed serial data transmission of the advantages and challenges, and introduce the most popular high-speed serial data transmission system structure—8B/10B SerDes. We study the process of interconnect signal integrity issues, focusing on the domestic and international high-speed serial interface circuit design and implementation. Based on the electrical characteristic descriptions of RapidIO serial physical layer on its transmitter in specification version 1.3, combined with project needs, the specific design goals for the 0.13um CMOS transmitter is given.2. Circuit design of the transmitter. With the purpose of high reliability, we implement the design with CMOS and pass transistor logic without low-Voltage involved. In the serial to parallel data conversion module, we bring forward a new structure named multi-phase tree type, which inherits advantages of low speed devices requirement and low power consumption, and overcomes the shortcomings of 2N width of the parallel input data of tree type. As to drive and pre-emphasis programmability, we choose a tri-state differential structure that can provide 24x drive and 8x pre-emphasis capability, and finally achieve goals of optimal signal transmission.3. Layout design process of the transmitter. We work more on detailed layout optimization on matching, parasitic, noise, latch, and ESD protection to reach high performance and high reliability of data transmission. Finally, the simulation results with Hspice tool show that for a given 60cm backplane transmission line at 3.125Gbps transfer rate with 12x drive and 5x pre-emphasis, the swing of the transmitter output signal can reach 600mV, and its parameters include transition time and jitter meet the design requirements.