| With the development of information science and technology, the demand for video products is continuesly increasing. Driven by this demand, the digital video encoding/decoding, processing and transmission technology have been developed quickly. As a current main stream video compression standard, H.264/AVC has achieved a significant improvement in compression efficiency, image quality and network adaptability.The panel technology continues to evolve, high resolution and ultra-high resolution panels are widely used in television, personal computers, mobile phones, tablet PCs and so on. It is a challenge for the video codec to support the high resolution video. Because of the advantage of H./264/AVC in compression efficiency, image quality and network adaptability, the H.264/AVC high-definition and ultra high-definition codec has been a hotspot of current research. Due to the data dependency in intra prediction and entropy coding algorithm, it is hard to improve the encoder by directly increasing hardware. Both intra prediction and entropy coding can become the bottleneck of the video encoder. In this paper, the data dependencies of the intra prediction and entropy coding are well studied. Many new technologies are proposed to improve the original algorithm; architecture with hardware multiplexing method is proposed to reduce the hardware cost. The experimental results show that our design can chieve higher design efficiency than previous work, and can support4Kx2K@30fps real time encoding.The main work of this paper includes:(1).Achording to the characteristics of the H.264/AVC intra frame encoder and the actual application, a macroblock-processing based architecture with for pipelined stages is proposed in this paper. This architecture has fully takon account of the practical application of input and output. The clock for intra prediction and entropy coding are also well designed to achieve a balanced system.(2).To release the data dependencies in the luma4x4sub-block prediction,4x4block scanning and mode co-reorder is proposed. A16-pixel per cycle process engine is proposed reduce the clock cycles for the4x4sub-blocks prediction path. For the four mode of16x16luma and chroma8x8prediction, common characteristics are well analyzed, architecture with hardware multiplexing method is proposed. These technologies greatly reduce the cycles of intra prediction and hardware costs; The design efficiency of intra prediction can also been improved. (3).To support the high throughput of intra prediction, the transformation and quantization for the H.264/AVC Intra encoder are also been optimized. In this paper, The DCT/IDCT is implemented by the butterfly fast algorithm. The multiplier used in quantization and dequantization are replaced by constant multiplier to achieve higher operation frequency.(4).The entropy coding is bit-related in H.264/AVC standard. A two-stage architecture of the CAVLC encoder is proposed to make the scan and encode work simultaneously; a paralleled scan engine which can scan two coefficients at one cycle is proposed. In the same way, a paralleled level encoder is proposed to accelerate the speed of encode engine. Two Run_before symbols are encodedsimultaneously with level. A fine bitstream packer is also well designed to pack all the codeword generated by the encoder.(5).The intra-only encoder is designed as IP. The input and output of this IP is well considered to make the encoder been easily implemented for real application.The H.264/AVC Intra-only encoder is implemented in Verilog HDL, synthesized using SMIC0.13um standard CMOS technology. Compared with some of state-art intra frame encoder, this design has higher design efficiency, and can support4Kx2K@30fps real-time encoding. |
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