Nand Flash Memory Chip Packaging Technology And Reliability

Stacked Die assembly technology is an ideal solution to a NAND product with higher capacity and lower profile, which meets the requirements of miniaturization and portable of product. But the further development was subjected by many factors, the biggest problem is package structure design, process yield and reliability performance, these issues have been the bottleneck of NAND assembly industry. Therefore, solving these problems quickly and effectively can enhance the capability of domestic NAND assembly industry, and it will benefit us very much.Based on the technical and process capability of domestic NAND assembly industry, this thesis submits a proposal of new 8-Die Stacked package structure, define and optimize the solution of process and reliability, we would like to make some contribution to our NAND assembly industry.The major tasks of this thesis are,1. Submit a proposal of new 8-Die Stack LFBGA package structure of NAND product. After reviewed the package criteria of JEDEC's definition, we would like to design a package which contains 8 pieces of NAND flash die in a dimension of 20mm*16mm*0.9mm.2. Submit a proposal of assembly process solution of 8-Die Stack NAND. After defined the preliminary assembly process proposal, We applied DOE method to optimize the parameters and material to decrease these defects (die crack, die chipping and gold wire bond lift) which comes from assembly process. We want to find a good solution to improve the process yield, and achieve cost reduction, increase the capacity of competition of NAND assembly industry.3. Submit a proposal of reliability optimization solution to 8-Die Stack NAND product. We applied DOE method to improve the Kirkendall Void and Delamination to enhance the reliability performance.