The Design And FPGA Implementation Of GPS Baseband Processor

With the advance of wireless communication technology, Navigation technology has entered every aspect of people's living and working. Integrated circuit has been developed rapidly, the SOC technology has become one of the most important directions. This article take the need of wireless combo SOC chip as background, focus on GPS navigation system ,discuss and design one of the processors– GPS baseband processor.Starting form the point of view of GPS intermediate-frequency digital signal processing, we setup Matlab simulation environment and discuss several capture algorithms of GPS signal and compare algorithm complexity of each other. In the paper, the VLSI feasibility and hardware resources consumption is considered carefully, we presents a rapid acquisition algorithm which is base on the doppler frequency capture in frequency domain and code phase capture in time domain. The Matlab simulation indicate that processor adopting this type of depression algorithms can save many correlator resources and capture satellite in 1 second, reducing the chip area and saving the power consumption. It is optimal to the SOC chip.The baseband processor realized function of tracking in full hardware. There are 8 identical tracking channel, using CORDIC algorithms to implement phase detector in frequency locked loop (FLL), phase locked loop (PLL) and delayed looked loop (DLL), using digital filter and numerical controlled oscillator to synchronous demodulation IF signal. In the paper we lift a hardware component module and detailed hardware module design, and discusses the feasibility of the program and the links between modules.In the verification of GPS baseband processor , we take 30 second inter-medium frequency samples data, Use Modelsim to simulate the whole RTL level circuit. Use Quartus to process logic synthesis.