Research On Key Fabrication Techniques Of Gate All Around Nanowire MOS Device

With the development of large-scaled integrated circuit, it is necessary for MOSFET to continue scaling down. As the feature size of MOSFET is scaling down to the end of the roadmap, severe short channel effects will happen. Gate-all-around (GAA) Si nanowire device structure is regarded as the most promising device structure that can scale the feature size of MOSFET to the end of the roadmap, due to its excellent gate control capability and greatly improved transport property.To fabricate Si nanowires, we have fabricated sub-100nm Si fins by e-beam lithography, hard mask trimming and spacer technique, respectively, which lay a foundation for the fabrication of Si nanowires. Moreover, we have proposed trimming + spacer technique to further improve the quality of spacer defined Si fins.Subsequently, How to fabricate uniform and straight Si nanowires. The impact of fin-define technique, sacrificial oxidation, and nanowire channel orientation on the line edge/width roughness (LER/LWR) characteristics has been systematically studied.Finally, How to fabricate cirlular Si nanowires. Si nanowires have been formed by sacrificial oxidation of suspended Si fins. The impact of oxidation temperature, original Si fin shape and oxidation time on the cross-sectional shape of Si nanowires has been systematically studied.