Design Of Reconfigurable Linear Array Processor Architecture For Intensive Dat Parallel Computation

In recent years, communications and multimedia technologies are emerging characterized by intensive data parallel computation, which makes higher performance requirements. Array processor is being the focus of embedded video field because of its excellent data-parallel computing performance, better flexibility, lower power consumption and smaller area. Array processor can be divided into two types, square array and linear array based on processing element (PE) array interconnection structure. Thanks to the 2-D interconnection network, suqare array has lower communication overhead and easy to map the 2-D image. However the complex interconnection makes it difficult to expend for throughput improvement. Linear array has a simple 1-D interconnection structure which is easy to expand for high throughput. But the inter-PE communication overhead is larger.We design the reconfigurable linear array processor architecture (RLAP) with the advantages of both two types. RLAP retains the benefits of traditional linear array such as high throughput and easy to extend. Meanwhile it reduces the communication overhead among PEs. Through instruction the interconnection structure can be configured into three kinds of block mode for three sizes of data blocks in video coding standard. It's convenient for the mapping of video coding algorithm.This paper describes the RLAP system components and parallel technology, use verilog language to complete the RTL level design, map and run a number of common video compression algorithm, through logic synthesis to evaluate the system area and power consumption. Experimental data show that the reconfigurable linear interconnect structure enhance the system performance while not increasing a great deal of area and power overhead. RLAP still has the advantages of low power consumption and small size as the linear array processor.