Research Of Signal Processing Technology In The High Resolution Seismic Data Acquisition

As an important part of geophysical observation, Seismic observation is the basicpart for the development of seismology and physics of the earth. For the vibrationobservation, huge dynamic range and wide frequency band are the main technicalcharacteristics, which use the seismometer and seismic data acquisition as the keyequipments. Seismic data acquisition is the important part of the digital earthquakeobservation system, which with the main function, converting the analog signals fromseismometer to digital signals. The level of analog to digital converter largelydetermines the quality of observation data. Therefore improving the performance ofseismic data acquisition is very necessary and has a lot of practical and strategicdemand.The research of signal processing in the seismic data acquisition is the maintarget of the essay. With the research in analog to digital converter of the researchersin the relative field, we will go deep into the research of signal processing section,then we will also try to design and verification the parameters of the Δ-Σ modulator.To change the sample rate, we will decimate and filter the output signals of the Δ-Σ ofthe AD converter. Meanwhile it has achieved fast and accurate way to process thedigital signal, also consists a high resolution and stability seismic data acquisitiontogether with the analog-digital convert circuits.Using the analog to digital converter which consists of Δ-Σ modulator and thedigital filter is a mainstream technology to achieve high resolutions seismic dataacquisition. Most of AD converter chips with high resolution adopt this technology.To test on the feasibility of the high resolution seismic data acquisition, we will use athird-order16bits Δ-Σ modulator design AD conversion circuit，since there is nosingle ADC chip with more than24bits resolution. Considering the conveniences onthe implementation of the circuit, we use active integrator circuit which based onoperational amplifiers to design the Δ-Σ modulator. Before design the test circuit, weneed to simulate the Δ-Σ modulator with the simulink tool, then add the windowfunction and FFT convert to the output data of DAC. Meanwhile we will alsodevelopment a multi-order FIR decimation filters for the output data stream, and then add window function, FFT convert again, after that experiment, check that if changesof the spectrum in both cases are same with the expectation. After simulation, we candetermine the main parameters of the Δ-Σ modulator, and then select the suitableoperation amplifiers,16bit ADC and DAC chips to design the test circuit andcomplete the PCB board depending on the above parameters, which with the logiccontrol circuit designed by the CPLD chip, and48000sps as the sampling rate. Savethe output data of the testing and debugging the circuit, and spectral analysis on thesedata indicate that the resolution of the test circuit is close to the current excellent24-bit ADC chip.It has designed a set of FIR digital filters in the article, which used to filtering thequantization noises of output data streams from Δ-Σ modulator, and converted thedata streams with sampling rate48000sps to the ones with the desired sampling rate.It also has verified the applicability of the FIR filter, by using the FIR digital filters toprocessing output data of the test circuit.