Based On The Third-order Sigma - Delta Modulator Implemented Since The Bias Spread Spectrum Study Of Phase-locked Loop

The size of device is continuously decreased as the integrated circuit technology is improved. EMI issue becomes more and more serious because the space between chips getting closer. In order to resolve EMI issue, spread spectrum PLL is developed.This thesis does research and design on spread spectrum PLL. It adds a triangular wave module on the 3rd order Sigma-Delta modulator of Fractional N PLL. Such change can realize controllable spread spectrum function. There are two types of spread spectrum in this thesis:one is center spread, spread spectrum amplitude can be±0.25%,±1%,±1.75%,±2.5%,±3.5%,±5%; the other is down spread, spread spectrum amplitude can be -0.5%,-2%,-3.5%,-5%,-7%,-10%. This thesis uses self-biased structure in the loop design, then the supply voltage can be only 1V power and it eliminates reference current generating circuit. The low pass filter is realized by on chip resistor and capacitor. An active resistor is used in the loop design. The self-biased loop can be implemented with only one charge pump.This thesis gives introduction to jitter and phase noise. It also does preliminary research on the optimization of each module’s parameter to decrease jitter and phase noise.The chip was designed and taped out based on SMIC 90nm Logical process. The test result shows very good performance.The PLL is stable at all through the output frequency range (from 62.5MHz to 1.6GHz). Peak to peak value of period jitter with no spread spectrum is less than 200ps.The radiant energy is attenuated with more than lOdB at maximum spread spectrum.