Study On SiP Reliability And Failure Analysis Technique

System in Package (SiP) is an important technology able to assemble multiple activeelectronic components of different functionalities in a single unit systematically, providingmultiple functions as a system or sub-system. A SiP may optionally contain CMOS ICs, RFICs, passives, MEMS, optical components, and other packages and devices. It is soprospective that has attracted pervasive attention because it provides integration flexibility,faster time to market, fine processes compatibility and lower R&D cost.Especially in the United States, Europe and some Asian developed countries, researchon design, manufacturing processes, and reliability for SiP is in far ahead of domestic.However, the domestic market also has a huge demand for SiP, we face serious challenges indefect diagnosis and failure analysis technique, and the studies of reliability just stay in thesimulation stage. Therefore, it’s of use and importance to study the reliability and failureanalysis technique for developing SiP technology.In this paper, we focus on searching the right defect location and failure analysistechniques to improvement the reliability of SiP. Different packaging structures used for SiP,including stacked die package, package on package (PoP) and through silicon via (TSV)interconnection, and corresponding common defects are analyzed. In this paper, fouradvanced failure analysis techniques have been introduced, including3D X-ray microscopy,lock-in thermography (LIT), magnetic microscopy and FIB.Finally, two cases of failure analysis in typical SiP devices are shown. One is solder jointdefect analysis of PoP and another is ESD failure in stacked die package. Not only3D X-rayand magnetic microscopy technology are applied to the cases, but destructive physicalanalyses are performed for result contrast and illustration. Assisted verifications with casesprovide a reference for exploring the best resolution for SiP different failure modes.