Design And Implement Of The ARM JTAG Emulator

ARM processors are used in embedded eletronical product widely, especially incommunication, industry control, and automatic, which became the major processor inembedded electronical product. As part of the development tool chain, ARM JTAGemulator is the very important to efficiency and difficulty of both hardware andsoftware development and affects product stability and roburst.Now, some JTAG emulators are used in practice. Near all of the high performanceemulator are developed by oversea tool providers, these are too expensive to generaldeveloper, small or tiny company. Some JTAG emulator with low price can’t meet therequirements of larget scale software development. These products don’t support highspeed program downlowd, hardware breakpoint, wachipoint, FLASH programming andetc. This subject focus on the problems mentioned ahead, provide a solution to designand implement the ARM JTAG emulator after study ARM EmbeddedICE technonogy,GDB debugging technology, RSP protocol, μC/OS-II and LwIP and etc. This JTAGemulator is designed base on AT91SAM9260, supporting ARM7and ARM9serialprocessor core and JTAG clock rate programming, with the communication infertaceincluding10/100M auto-adapt Ethernet, USB and RS232. The key points involved inthis subject are described below:1. Debugging theory of ARM JTAG, including TAP controller, EmbeddedICElogic, and boundary scan principle. Then provide the design thought, scheme,and method to ARM JTAG emulator.2. Base on ARM JTAG theory analysis, design requirements and designspecification was provied. AT91SAM9260chip is selected as the processor.This hardware scheme has several good feathures, supporting target JTAGinterface voltage auto-adapt, supporting wide input votage range, supporting10/100M auto-adapt Ethernet interface, RS232serial communication and USB.After the scheme given, some critical schematic designs are given in details.3. ARM JTAG software system is built on μC/OS-II and LwIP, support highspeed download. One high performance JTAG macro instruction process logic was designed and implemented to achieve1Mbytes download speed and JTAGclock rate programming, the static function interface and dynamic running flowdesign about RSP protocol, GDB command parser, JTAG debugging commandand etc are introduced in details.