Study Of Flash Memory Based On High-K Material

With the continuous development in electronic information society, the requirement for storage technology is increasing in the semiconductor industry. To further increase storage density, the feature size of memory device is scaling down continuously, driven by Moore’s law. The scalability of flash memory based on conventional poly-silicon floating gate (FG) will bring in serious reliability issues, including cell-to-cell coupling and SILC-induced charge loss. To solve these problems, charge trapping memory based on discrete charge storage technology is proposed. Moreover, the study of replacing poly-Si by metal as floating gate to improve the memory performance is also performed by more and more researchers. Taking the advantages of high-K materials with high dielectric constant into account, single high-K layer and/or multi high-K layers engineered energy band structures have been introduced into memory structure to form performance-optimized memory device.The high-K materials can make the memory device realize low voltage operation and excellent reliability. In this work, to further improve the performance of charge trapping memory and metal floating gate memory, after the improvement of HfO2performance by process optimization, high-K materials were introduced into charge trapping memory and metal floating gate memory, and the influence of high-K on memory performance was also investigated. This work consists of three parts:firstly, to improve the trap density of HfO2as trapping layer, the growth process of HfO2film by ALD is studied; secondly, to improve the performance of charge trapping memory, HfO2, Al2O3and HfAlO were deposited as trapping layers by ALD, then the effect of annealing on A12O3blocking layer was investigated, and an available way, namely "pre-annealing treatment to blocking layer", which can improve the performance of memory device was proposed; Thirdly, to increase the storage density and decrease the power consumption, high-K materials as tunneling layer and/or IGD were introduced into the TaN floating gate, and the effect of SiO2/HfO2dual tunneling layer on memory performance improvement was discussed.Experiment results demonstrate that the optimization of high-K deposition process and the introduction of high-K into charge trapping memory and metal floating gate memory can improve the memory performance, which is beneficial to realize3-dimension (3-D) and multi-level-cell (MLC) technology. This work provides a way to improve memory performance from the viewpoint of optimizing high-K deposition process and device structure and it’s of important guiding significance.