Research And Design Of Deterministic Background Calibration System For Pipelined ADC

Analog-to-digital converter(ADC) plays a special role of converting outside analog signals into digital signals in mixed-signal systems. As a representative of medium and high speed ADCs, pipelined ADC makes a good compromise among speed, accuracy and power dissipation, and it is widely applied in many fields. So, pipelined ADC has been an active topic for analog/mixed-signal IC design. With improvement of integrated circuit process, digital circuit develops fast, but analog integrated circuit is lagging behind in the rate of growth, thus ADC has become the bottleneck of the development of mixed-signal systems. The emergence and extensive use of digital calibration techniques make the accuracy requirement of the analog signal convert to digital domain in ADC design. With this technology, the adverse impact caused by low voltage and transistor intrinsic gain can be alleviated in analog circuit design, and the power consumption of high-accuracy ADC can be greatly reduced.Different from general digitally assisted pipelined ADCs which replace traditional feedback amplifiers with open-loop amplifiers, this dissertation adopts higher current efficiency push-pull common source op-amp. High order nonlinear errors introduced by push-pull common source op-amp are eliminated by establishing accurate model of the op-amp transfer function. Firstly, a calibrationsub DAC is added to pipelined stages. Thus, the interpolation endpoints will be obtained by injecting digital test signals to calibration-sub DAC periodically. Then cubic polynomial functions are applied to fit op-amp transfer function. To calibrate the capacitance matching error introduced by technology limitation, Karanicolas technology is adopted.In order to verify the effect of this calibration algorithm, a 12-b, 10-MS/s pipelined ADC core circuit is presented, and push-pull common source architecture is used in the first four stages. Mixed simulation results show that, with digital calibration, the ADC differential nonlinearity and integral nonlinearity are improved from(-1~1.75) LSB and(-7.9~7.6) LSB to(-0.75~0.5) LSB and(-0.9~1.2) LSB. For a 4.88-MHz sinusoidal test signal, with calibration, the ADC spurious-free dynamic range and signal-to-noise-distortion ratio are improved from 44.3 d B and 38.8 d B to 82.0 d B and 70.7 d B, respectively. After calibration, the effective number of bits improves from 6.2 bits to 11.5 bits. The total power consumption of ADC is 89.5m V,in which the digital circuit accounted for 10.0% of the total power. Only 11264 sampling periods are needed to complete estimation of all correction parameters, so this algorithm has an advantage of short convergence time.