Research On Low Power Technology Based On Multi-Bit Flip Flop

With the development of Integrity Circuit in the process and the characteristic size reduced continuously, IC design has entered the design phase of SoC ultra deep submicron and it also has higher requirement for area, performance, power consumption. With so many products especially the continuous upgrading of handheld devices, low power technology has become crucial technical constraints and rapid development of such products. To further reduce the power consumption of the chip, the use of Multi Bit flip flop(MBFF) has been shown to be an effective design technique in the back-end design flow at present. With respect to a pair of Inverter shared with MBFF, the size of the capacitive load is reduced, thereby reducing the chip’s power consumption. Although the use of MBFF can effectively solve the power problem, but since the MBFF supported by EDA tools is still not so perfect, the current IC industry takes lots of manual intervention in the limited EDA tools of back-end physical design to complete the merging of MBFF.This paper will be based on the new generation of Cadence digital back-end physical synthesis tool Innovus to giving comprehensive functional testing and validation for the new feature of MBFF. Also the experiment will apply the Samsung 28nm process library into four actual design, and then using three different design flow process of Innovus(Both, Merge Only, None)to explore how the use of MBFF in the flow influence the timing, power consumption, area, routing. According to the result of the different flow, analysising the advantages and disadvantages of using MBFF.