Data Memory Structure Design Of Coarse-grained Reconfigurable Processor For Radar Applications

Due to the combination of flexibility and efficiency, reconfigurable processor is suitable for implementing various computation-intensive applications with high parallelism and large quantity of data, including radar signal processing. However, with the growing performance requirements of radar application, the computational resources of coarse-grained reconfigurable architectures increase exponentially.When the computing resources of reconfigurable processor work in parallel, it will need to read data from the on-chip data memory at the same time, which lead to frequent access conflicts and rapidly growth of on-chip data transmission time, as well as reduces the overall system performance. Therefore, how to set up an efficient data storage structure and high-efficiency management mechanism plays a very important role in improving the performance of reconfigurable systems.In this thesis, the key factors of radar kernel sub-algorithms are analyzed firstly. Aiming at the serious problems of access conflicts and low access efficiency, this thesis proposes a hierarchical memory structure and data management strategy based on linear varying step-size for radar sub-algorithms. First, the data access processing of radar kernel sub-algorithms in coarse-grained reconfigurable processor is analyzed, and two data access features of radar kernel sub-algorithms are summarized:high parallelism and one-dimensional linear leapfrog access mode. Then the design and optimization of data management scheme is carried on from two aspects. In the aspect of hardware architecture, by using multi-bank memory in the array,and the bank number of memroy is confirmed through theoretical analysis and C model simulation. In the aspect of management strategy.by establishing the logical mapping strategy between the reconfigurable arrays and the multi-bank memory, our design successfully reduces the access conflicts when the tasks assigned on different arrays fetch the required data in parallel and achieves higher throughput. Consequently, the data access performance of the reconfigurable system is improved.Under the SMIC 40nm technology, the circuit run at 500MHz. Experimental results show that, based on the hierarchical memory structure and data management scheme designed in this thesis, the on-chip data access performance upgrade to 27.5%-58.0% and the memory size is 770Kbytes. The memory access performance can be increased by 35% in the comparison to the representative PMA(Parallel Memory Architecture) for radar sub-algorithms. For example, the access performance for 256-point to 64k-point FFT can be improved nearly 26.09% to 54.60% compared to PMA. Compared to the two reconfigurable architectures of ADRES and Laysers CGRA, RASP achieves nearly 4 and 3 times respectively in normalized performance.