Design And Implementation Of High-Speed LDPC Code Decoder Based On FPGA

With the continuous exploration of space science and technology and the rapid development of channel coding technology, digital communication systems become more complex, the transmission rate and bit error rate of the communication equipment have become increasingly demanding. At present, the channel coding technology is relatively backward, and can not achieve the requirements of high-speed transmission of digital communication, it is necessary to research channel coding technology, particularly for coding and decoding technology design and realization. The LDPC(Low-Density Parity-Check Codes, LDPC) is a milestone in the field of channel coding in recent years, and its excellent performance and parallelism of the error correction decoding algorithm so that it is used in a digital communication system widely. Nevertheless, the current LDPC decoder of being implemented in hardware there are still relatively low speed, poor performance and lack of flexibility and so on. In view of this, the design and implementation of high-speed LDPC code decoder on FPGA has great significance for the practical application.This paper studies high-speed LDPC code decoder implemented on the FPGA. First, The basic theory of LDPC code and its decoding algorithm are studied in depth, analyzed the probability domain BP algorithm, the log domain BP algorithm, minimum and decoding algorithm and improved minimum and decoding algorithms, and simulation analysis and comparison the decoding performance of these decoding algorithm in order to find out the decoding algorithm design and implementation on FPGA suitable and optimize it for high-speed decoding improve. Then, based on the high-speed demands decoder given herein, elect easy to design and implement the quasi-cyclic LDPC code and converted into a block quasi-cyclic LDPC code according to their pattern, with high degree of parallelism in the way of high-speed decoding device design, including updating the decoded data input and output modules, variable nodes and check nodes, decoding information stored, etc., to improve decoder throughput design methods were optimized, Such as efficient use of hardware resources, system high clock stability, reduce the maximum number of iterations, etc. Finally, on the development of the company's board is equipped with Xilinx Virtex5 series FPGA chip write Verilog hardware decoding program, and implemented CCSDS recommended(8176,7154) LDPC code shortened speed decoding, including data input-output control, translation code data storage efficiency, variable node unit functional modules and check node unit each function module, and test verification in order to analyze its performance.In summary, research and analysis by the relevant principles of LDPC codes and decoding algorithm, using MATLAB simulation, using FPGA for high-speed LDPC code decoder design and optimization, and write Verilog hardware for testing and analysis program. Test results show that the high-speed FPGA-based LDPC code decoder can achieve the requirements of the relevant indicators, in the case of basic decoding performance without loss, to achieve high speed the decoder's decoding 650 Mbps of single channel.