Backend Design Of Short-range Wireless Data Transmission Baseband Chip

With the increasing development of integrated circuit, the backend design of IC is gradually becoming important constraints of yield and cost. With the continuous decreasing of the feature size of IC process, IC chip extends its application in many fields. Nowadays, IC chip is widely used in smart electronics, wearable devices and medical. The applications in these fields urge that low power methods should be used in IC design. How to reduce power consumption and graduate performance of a chip becomes a key point in IC design.In the background of wireless digital communication technology, short-range wireless data transmission technology has got wide application in every aspects of social life, by virtue of its advantages of low power consumption, small areas, low cost and simple architecture. Based on the scientific research project of research group, this paper conducts the backend design of a wireless digital communication baseband chip. This paper introduces specific impletion of backend flow and expatiate on the problems and its solutions met in the backend flow.The main contributions of the paper include:1) Introduce the principle and flow of logic synthesis with the emphasis on low power synthesis technology——the clock gating method. Applying clock gating skill in the logic synthesis of wireless digital communication baseband chip, the power consumption of the chip is reduced from 52 m W to 38 m W, by 27 percent.2) Summarize the timing constraints of the circuit. Introduce the principle of static timing analysis in detail and the tool and its use briefly. This paper gives the method of solving violations in static timing analysis and solves the timing violations in backend tools successfully.3) Introduce backend design flow and layout design tools. Finish the layout design of wireless digital communication baseband chip by the use of astro, including floorplan of area and power, clock tree synthesis, place and route. Introduce the reason and solution of process antenna effect(PAE) and solve the PAE of this layout. After layout design, the static timing analysis is conduct on the netlist with parasitic parameters, problems are found solved by changing netlist and change the layout based the changed netlist. The areaof the final layout is 1.87mm×2.39 mm.4) Introduce the principle of formal verification and the physical requirements of the layout briefly. Formal verification is conduct between the final netlist and RTL coding. Design rules checking(DRC) and electronic rules checking is done on the final layout by the tool of Calibre to confirm the quality of the layout and make sure it can be taped out.5) Complete the package of the die. Functional test is conduct after package and the chip meets the requirements which are design to be.Revolve around the work above, this paper make comprehensive introduction of the principle, the utilization of tools and real practice of backend design of integrated circuit. In the procedure of specific impletion, thorough discussion and detail analysis are made on the problems met and corresponding solutions.