Study On Heterogeneous Multi-Core Systems With Mixed Work-Mode Reconfigurable Computing Units

With large data throughput and strong real-time demand, high density computing applications, such as image processing, scientific computing and big data analysis, have put forward a higher requirement on the processing capacity of microprocessor.Multi-core technology extends the development direction of processor from a single longitudinal development to horizontal development as well, which greatly reduces the difficulty of processor design, and has became a mainstream in the past ten years.Giving consideration to both the high efficiency and the flexibility of computing,reconfigurable computing is one kind of excellent computing architectures. Dynamic scheduling technology, as an important technology in processor design today, which can eliminate the data hazards, significantly improves the efficiency of processors.In the calculation,there are two typical calculation organization types: storage computing and stream computing. In storage computing mode, it's easy to realize the reuse of data, but it takes a lot of time in data transit; stream computing can hide the data transit time and greatly improve the computing throughput, but gives a higher pressure to network communication and storage bandwidth.Based on the above background, this thesis does some relevant research about heterogeneous multi-core system that supports mixed computing modes. The main works are as follows:Firstly, the thesis introduces the original architecture of our heterogeneous multi-core computing system (HMCS), and transforms the target system with two-level computing architecture. Meanwhile, to make the HMCS much more standard, new working mechanism and top-level instruction set are designed.Secondly, a main control unit for the HMCS is designed in the thesis. By introducing the technology of dynamic scheduling and register renaming, out-of-orderexecution and multi-issue in task instruction level are achieved. In addition, the parallel implementation of thread-level is explored to further improve the instruction launching ability of HMCS.Thirdly, a coarse-grained reconfigurable computing unit (RCU) is designed for the HMCS. As a reconfigurable computing unit, RCU can achieve a variety of functions and work in different modes. The architecture of RCU is also optimized for some common complex algorithms, such as matrix calculation, FFT and etc, reaching a good performance with limited resources.Finally, the design is tested and evaluated on a FPGA, and the experimental results show that the performance has achieved the performance requirements.