The Research And Design Of Adaptive Routing Algorithm And Bufferless Structure For Network On Chip

With the continuous development of integrated circuit design and semiconductor technology,more and more IP cores are integrated into single chip.The So C interconnection scheme based on traditional bus has many problems,such as poor scalability,difficulty of global clock synchronization and low communication performance,which is difficult to meet the performance requirements of multi-core chips.By applying the theory of distributed computer internetwork to the complex So C interconnect design,which can effectively improve the performance of inter-chip communication,and it is proposed and hopeful to become the interconnection technology in future multi-core chips.In this dissertation,the key technologies of the No C routing algorithm,network topology structure and hierarchical architecture are researched.Aiming at the requirements of high performance applications as well as the low cost applications,the buffered adaptive No C and the bufferless No C are designed and implemented respectively in this paper.Based on the THNo C and SRNo C topologies,an adaptive routing algorithm(adaptive_STR)is proposed in this thesis.The THNo C and SRNo C topologies employ the traditional 2D Torus and 2D Mesh as their backbone,an extra Tile Interconnection Manager(TM)is added between adjacent rows and columns,thus,the packet can be reached between two adjacent rows and columns through single hop,which greatly reduces the diameter of network.There are two important features for this algorithm: the number of hops for any routing paths is not more than 2 hops;the routing paths can be adaptively selected according to the real-time load of the network.The routing algorithm mainly consists of the routing algorithm of the router and the TM's output port allocation strategy.Using the synthesized Verilog RTL to code the proposed No C systems,the network size are 8×8.Meanwhile,use the Verilog RTL to build a clock-accurate performance evaluation platform.It can achieve the network performance evaluation for different No C systems under the random,hotspot,transpose,bitreversal,shuffle,butterfly six traffic distributions.Compared with the existing No C systems,the experimental results show that the proposed A_str_THNo C and A_str_SRNo C can increase the network throughput by an average of 58.3% and 55.3%,respectively.And the hardware cost increase just by 8.7% and 5.8%,respectively.The bufferless No C system is also researched and designed in this thesis.A network topology named SPmesh(Shared-Permutation mesh)is proposed.It employs the 2D mesh structure as the backbone,and a Shared-Permutation unit is added between the router nodes,each of the four routers as a group to share a SP.The SPs increase the diversity of routing paths,reduce the flits' transmission delay and the number of deflection times and improve the bufferless routing performance.And a bufferless routing algorithm named SPBLESS based the proposed SPmesh topology is proposed,which includes router routing algorithm and the SP output port allocation strategy.Meanwhile,this thesis improved the traditional livelock avoidance strategy OF(Oldest-First).Using the synthesized Verilog RTL to code the proposed SPBLESS as well as the traditional mesh based bufferless No C system,the network size are 8×8.Compared with the traditional mesh based bufferless No C systems,the experimental results show that the proposed SPBLESS can reduces the flits' average deflection number by 26.7%,increases the network throughput by an average of 13.1% and reduces the total network load by 27.6% averagely under six synthetic traffic distributions.And the hardware cost increases by 19.0%.