The Design And Implementation Of Chaotic Sequence Generator Based On Residue Number System

Chaotic pseudo-random sequence has been extensively and deeply studied in recent years for its virtues,such as sensitive f-or initial value,bounded numeric and non-periodic.These features make it valuable for communication and encryption system.The performance of traditional digital chaotic sequence generator will decease owing to the finite word length effect.Although there are several ways to ameliorate this effect,the sequence still suffer from period reduction and low-generate rate.Furthermore,the large iteration bound and long critical path of the traditional chaotic map lead to a low system throughput that can not meet the requirement of high data rate applications.To deal with these problems,this thesis presents a method for generating chaotic sequence based on the Residue Number System(RNS)and permutation polynomials over finite fields.Thanks to the property of RNS,several short period sequences can convert to a long period digital sequence.These short period sequences are generated by a couple of permutation polynomials.This method could reduces the hardware costs and improves the system clock frequency.The main work of this thesis are listed as follows:(1)A algorithm for high-speed and long-period chaotic sequences generation based on permutation polynomials and residue number system is presented.(2)A construction method of permutation polynomials is explicitly given in this paper,besides,the hardware implement of Chinese Reminder Theorem(CRT)is optimized.(3)An all-lookup table implement structure has been proposed to reduce the hardware costs and accelerate the generation speed.(4)The proposed sequence is further applied to theimage encryption domain,and the simulation results show the encryption performance.The sequence based on permutation polynomials and residue number system has a deterministic period,and the period length can easily reach to 2100 in existing platform.The hardware consumption is low and the implement structure is very simple.The generator is multiplier-free,and it only costs 20 BRAM and a small amount of other logic resources.Moreover,the hardware implementation results show the system clock frequency can easily reach to 395Mbps on FPGA XC7Z020.The sequence can be used in the field of image encryption.It can be proved that the key space is considerable large.Using only a subset of the permutation polynomials,the key space is more than 4.5x10[2].The results of NIST testing show that the sequence has good stochastic property and encryption performance.