Design Of 120-Gb/s Multi-channel Optical Fiber Data Transmission ASIC For High Energy Physics Experiment

The high-energy physics experiment is an important basic physics experiment to explore and study the interaction between material composition and particles.The massive information transmission and anti-irradiation requirements at the front end of the detector pose a severe challenge to the design of high-speed data transmission links.High-speed multi-channel optical fiber data transmission chip has obvious advantages in high-speed information transmission due to its high bandwidth,high density,low power consumption,anti-irradiation and other characteristics,and has gradually become the first choice for data transmission design of detector front-end in high-energy physics experiments.The main research work in this paper is to design a 120-Gb/s multi-channel optical fiber data transmission ASIC adopts SMIC 55nm RF CMOS technology,which is applied to the field of detector front-end data transmission in high-energy physics experiments.The specific research contents and innovations of this thesis are shown in the following:Firstly,a new pre-emphasis circuit structure is proposed:an RC resistor-capacitor pre-emphasis structure is added to the tail current circuit of the output driver stage to compensate for the signal bandwidth attenuation caused by the bond line inductance,PAD capacitance and VCSEL laser load.Reduced signal jitter and optimized eye diagram.The electrical test results show that after using the pre-emphasis circuit structure,the laser output eye diagram becomes clear and the opening degree is expanded.The overall jitter is 25.1 ps,the rise time is 68.4 ps,and the fall time is 68.0 ps and achieved the expected goal.Secondly,two methods for designing the anti-irradiation performance of the enhanced chip are proposed.First,the core analog circuit of the chip uses a larger finger MOS tube to resist the total dose effect.Second,the I2C digital control module uses a three-mode redundant circuit structure.Counteract the single particle flip effect.After using these two methods,the anti-irradiation performance of the chip is significantly improved.Thirdly,a method for improving the signal bandwidth by using equalization technology and shared inductor technology is proposed.The input circuit adopts a continuous time linear equalizer(CTLE)structure to compensate the high frequency brought by the transmission line attenuate,the bonding line inductance and the PAD capacitance on the PCB.the limiting amplifier stage uses a shared inductor topology to further increase the signal bandwidth.The post-simulation results show that with two bandwidth extension techniques,the-3dB bandwidth is increased from 6.8 GHz @10 Gb/s to 11.3 GHz @ 10 Gb/s at typical process corners.Fourthly,it is proposed to reduce the overall power consumption of the chip by using a low-voltage CMOS process and reducing the power supply voltage:the chip uses SMIC 55nm RF CMOS technology,the analog core circuit power supply voltage is 1.2 V and 2.5 V,and the digital control circuit power supply voltage is 1.2.V.The measured power consumption of the chip shows that after using these two methods,the measured typical power consumption(output current eye amplitude is 2-7mA)is 32.1 mW/ch @10 Gb/s,which is lower than the typical power consumption of commercial chips of the same specification(46 mW/ch @ 10Gb/s).At present,the chip has been successfully streamed and completed the actual measurement,the overall jitter,eye diagram quality,power consumption and other performance reached the expected indicators,followed by the development of optical testing and irradiation testing.