Design Of Lower Esophageal Sphincter Electrical Stimulator For The Treatment Of Gastroesophageal Reflux Disease

Gastroesophageal reflux disease(GERD)is defined as “a condition which occurs when the reflux of stomach contents causes troublesome symptoms and/or complications”.The prevalence of GERD is increasing in recent years.As the medical burden becomes increasingly heavy,the treatment of GERD has become a research hotspot worldwide.The traditional medicine method has the problem of treating symptoms without treating the root cause and easy to relapse after stopping the medicine.Surgical treatment is traumatic,postoperative dysphagia,abdominal distension and other complications.Lower esophageal sphincter(LES)electrical stimulation therapy can stimulate the LES tension by voltage or current mode to restore the antireflux effect of LES,providing a new treatment for GERD.This thesis proposes a current stimulator with TSMC 0.18?m CMOS process for the gastroesophageal reflux LES electrical stimulation systems,which utilizes highly integrated design in analog integrated circuit technology in order to decrease the volume of the in-body stimulator.Compared to already-published research,the proposed stimulator has ensured good performance as well as an obvious reduction on the size of circuits.Firstly,the principle of the LES electrical stimulation therapy,pulse patterns and stimulate parameters are introduced.The current stimulation mode is selected to achieve precise control of the amount of charge injected into the tissue,which is closer to the natural process of tissue stimulation.The control of the stimulation current is achieved by a voltage controlled current source consisting of an operational amplifier and resistors.Then,the operational amplifier is analyzed and designed.Operational amplifiers with different loads and structures are introduced.A two-stage structure is adopted in the operational amplifier.More concretely,the first stage uses cascaded differential inputs to ensure a high gain while the second stage employs a common-source configuration.Additionally,the bias voltage is realized by the first-order bandgap reference,which can effectively reduce the influence of temperature.Miller capacitance and zeroing resistor control the pole-zero,to achieve sufficient phase margin,ensure the stability of operational amplifier.Based on Howland methods,optimization of the voltage-controlled current source is also realized,which has improved the stability of currents.The rise time of the voltage-controlled current source is 0.73?s,the mismatch current is 8.435?A.The overall size of the designed chip is about 320 ?m x 250 ?m,with the power consumption of about 2.53 mW.