Design And Implementation Of IOT High Energy Efficiency Processor

With the development of technologies such as communications,chips and other technologies,as well as the concept of the Internet of Everything,the Internet of Things will usher in rapid development.According to an organizational forecast,by 2025,the number of endpoint devices for the Internet of Things will reach over 70 billion,which puts forward low-cost requirements for endpoint devices.Since endpoint devices are often untethered,they must be very inexpensive to maintain and operate;And such IOT endpoint devices are generally small and powered by batteries.By reducing the power consumption of the endpoint devices to increase the service life of the endpoint devices,the maintenance cost can be reduced.The endpoint devices are generally composed of a sensing module,a processor,and a radio frequency module.The processor and the radio frequency module consume most of the energy of the terminal device.The processor usually completes the application processing,security processing and communication processing.The communication processing occupies most of the processor power consumption,which requires reducing the power consumption of the baseband processing.Now most embedded processors only use low power consumption as an evaluation indicator and do not consider energy efficiency.Low power consumption indicators cannot accurately reflect the actual energy consumption of embedded processors.To solve the above problems,this study designed a dedicated processor with high energy efficiency.ASIP is used to analyze the characteristics of the baseband algorithm and to customize the acceleration instructions to improve the operating efficiency of the baseband algorithm,thereby reducing energy consumption.Accordingly,the kernel contributions of this thesis are as following.1.Analyze the feature information of the NB-IOT heart baseband algorithm and customize the acceleration instructions based on the feature information.2.The processor micro-architecture is designed,including the processor's pipeline level,dynamic branch prediction,multiplication/division function unit,memory architecture and so on.3.Based on LISA's advanced modeling language,the processor is modeled and the function of the processor's instructions is verified through the simulation environment.4.A comprehensive tool was used to evaluate the processor's main frequency,area,and power consumption,and the NB-IOT baseband core algorithm was used as a benchmark to evaluate the processor's energy efficiency.Through the evaluation of the DC synthesis tool,the tatal power at 332 MHz is only 2.9 mW under the SMIC 40 nm process.Its energy efficiency is 1.36?J,nearly double that of some commercial processes.