High Performance Network-on-Chip For Cache Coherence Optimization

With the improvement of semiconductor manufacturing technology,more and more transistors can be integrated on a single chip.In order to improve the performance of the chip,designers integrate more and more processor cores and intellectual property(IP)cores into one chip.However,while multi-core system brings performance improvement,it also introduces new problems,including data transmission between multiple cores and cache coherence.In the field of on-chip data transmission,traditional single-core chips generally adopt bus structure.But it is difficult for bus to support large-scale,high parallelism and low latency data transmission required by multi-core chips,so Network-on-Chip(NoC)emerges as the times require.NoC mainly consists of network interface(NI)and router.A NI connects a local element and a router,responsible for data format conversion between them.In addition to connecting NIs,routers connect with each other to achieve data transmission between cores.The performance indicators of NoC mainly include transmission delay and maximum throughput.Multi-core chips also have the problem of cache coherence.Each private cache may store different data for the same address,which causes memory access errors,so cache operation needs to be constrained by cache coherence protocol.In coherence protocols,a node may send the same data to multiple nodes,so multicast communication is needed.If NoC does not provide hardware support for multicast,the transmission delay of multicast communication will greatly increase,while also increasing network congestion and reducing network performance.By supporting multicast with hardware,NoC can avoid sending the same data packets repeatedly,avoid wasting interconnection resources and improve network performance.Aiming at the multicast communication requirement of cache coherence protocol,this paper proposes a deadlock-free buffer unit for NoC routers.Based on this buffer unit,this paper proposes two routers supporting packet replication for deadlock-free NoC multicast communication.The high-performance router can replicate data packets from one buffer unit to multiple output directions at one clock cycle,which improves the bandwidth of the router and effectively improve network performance.The low-overhead router can only send out one flit from a buffer unit in one clock cycle,however its circuit overhead to replicate the data packet is small.The proposed routers are implemented in Verilog language,and its simulation environment is built in System Verilog.Experiments are carried out under various load modes.The results show that the proposed routers can effectively support packet replication,and its on-chip network can efficiently support multicast loads with low latency and high throughput.In the raytrace test program,the network latency of the two routers,compared with baseline router,decreased by 53.34% and 39.31% respectively.Router circuits are synthesized using TSMC45 nanometer technology.The results show that,compared with the baseline router,the circuit area overhead consumed by the two routers is 30.38% and 6.71% respectively.