Research On Decoding Algorithm Of LDPC-CC Code Based On Pipeline Decoder Architecture And FPGA Implementation

Low-density parity-check(LDPC)block codes,defined by their own parity check matrix with its sparseness,can be decoded by adopting the Belief Propagation(BP)decoding algorithm.There is little difference between the error correction performance of LDPC codes and Shannon limit.Convolutional codes are the codes whose encoder has memory function.In terms of error correction performance,block codes are not as effective as Convolutional codes.Low-density parity-check convolutional codes(LDPC-CC)are the LDPC codes with the convolution characteristics,whose check matrix has the same characteristics as LDPC codes.At the same time,they also have the memory characteristics of the convolutional codes,so both their encoders and decoders have unique architecture design and are worthy of further research.In this thesis,a construction method of the check matrix of the LDPC-CC codes is derived from a research and analysis of their concept and structure.Because the LDPC-CC codes check matrix,with its sparseness,is similar in characteristic to the LDPC codes,the BP decoding algorithm can also be used when the LDPC-CC codes are decoded.Meanwhile,because LDPC-CC codes have the advantage of convolutional codes and their check matrix contains memory characteristics,the constraint relationship between their variable nodes and check nodes is limited to a fixed length after encoding.Therefore,the LDPC-CC codes decoder can be designed as a pipeline in its architecture design.This thesis is mainly about a research and analysis of the architecture design of LDPC-CC codes decoder.A large number of simulation data are obtained by simulating the encoding and decoding of LDPC-CC codes.Based on the data,several key factors impacting the decoding performance of LDPC-CC codes,such as decoding algorithm,memory length and proportion factor,are analyzed.The decoder of LDPC-CC codes has two disadvantages: comparatively high in decoding delay and low in storage efficiency.So three improvement programs were discussed on the pipeline decoder of LDPC-CC codes in this thesis.One is to design a rule that causes the processors to suspend calculations—i.e.,partial verification is done by the sequence in which the processors make a hard decision.Another is to adopt the on-demand variable node activation schedule(OVA)and make some adjustments when the information of the check nodes and variable nodes is updated,which will not change the activation order of the check nodes.But as long as the check node activation requires a message,the variable nodes are activated instead of activating the variable nodes that will leave operating regions.The last one is to adopt a compact pipeline decoding architecture.This improvement can make neighboring operating regions overlap to decrease the total storage requirements of the decoder.In this arrangement,since the bits belonging to the overlapping regions are not yet ready for the next iteration,the Bit Error Rate(BER)is expected to increase.Simulation results show that the use of these three improved decoding algorithms can not only reduce the initial delay of the decoder,but also decrease the complexity of decoding,thereby improving the error correction performance of the decoder.After a further research and analysis of the LDPC-CC codes decoder,the overall hardware implementation architecture of the decoder is constructed in this thesis.In the Quartus II software,the Verilog Hardware Description Language(HDL)is used to input the hardware language program for each sub-module of the decoder.Then the PowerPlay Early Power Estimator tool is used to test the power consumption of the overall architecture of the LDPC-CC codes decoder by setting different frequency values,and finally analyze the related resources of the LDPC-CC codes decoder through the power consumption test results usage.The results show that,compared with the pipeline decoding algorithm,the OVA decoding algorithm is superior to the pipeline decoding algorithm in performance,although the use of logic units and registers have increased.Therefore,it is very valuable to sacrifice some hardware resources to improve the decoding performance.