Implementation Of Convolutional Neural Network Accelerator Based On FPGA In Intelligent Orthokeratology Matching Algorithm

With the rapid development of deep learning,neural network algorithm has been widely used in the field of image processing,especially in image classification,target recognition,image segmentation and other research area.The conventional matching method of orthokeratology(OK mirror)is that the ophthalmologists use the artificial way to segment the flattened area in the patient's corneal topographic map and carry out matching according to the flattened area.This artificial matching method is timeconsuming and inefficient,which is not suitable for large-scale popularization.In this paper,an intelligent matching algorithm based on neural network is proposed to segment the corneal topography map,mark the effective flattening area,and improve the matching efficiency of OK mirror.U-Net network is a kind of network evolved from the Convolutional Neural Network(CNN),which has made outstanding contributions to the biomedical image segmentation fields such as cell tracking,tumor location and so on.In the intelligent matching algorithm of OK mirror,it is a reasonable solution to use U-Net network to segment corneal topography.In academic research,the main neural network training and inference platform is CPU+GPU hardware platform,in which CPU is responsible for building the neural network and scheduling the network operation process,GPU is used to relieve the pressure brought by a large number of matrix operations in neural network.However,in the embedded application scenario,the power consumption,cost and other factors of the hardware platform need to be considered.CPU+GPU hardware platform is not suitable for mobile applications.Arm+FPGA heterogeneous SOC hardware platform can effectively make up for the deficiency of CPU+GPU hardware platform in the mobile end.It is suitable to deploy the trained neural network to the heterogeneous SoC platform and implement the inference task in the application scenario.The ARM microprocessor as the main processor controls the whole system,and FPGA as the coprocessor accelerates the operation of neural network.In the design scheme of neural network accelerator based on FPGA,the hardware circuit design methods such as loop unrolling and loop pipelining are used to increase the parallelism of hardware accelerator and improve the overall operation performance of hardware system by improving the utilization rate of hardware resources in FPGA.The accelerated design of convolution and pooling operation of u-net network is realized on FPGA.Finally,ARM+FPGA heterogeneous SoC Hardware Acceleration system is built in Digilent Pynq-Z1 development platform,in which ARM Cortex-A9 is the main processor and Zynq-7000 FPGA is the coprocessor.In the heterogeneous SoC Hardware Acceleration system,the embedded software development of U-Net neural network inference task is completed,in which the operating frequency of ARM is 650 MHz,and that of FPGA is 100 MHz.The experiment shows that the convolution operation is accelerated by 20.122 times,the pooling operation is accelerated by 32.684 times,and the operation performance of the hardware accelerator of the whole u-net network is improved by 19.749 times.It is an effective neural network acceleration method and provides an effective solution for the deployment of neural network applications at the mobile end.