Morphology and electronic properties of silicon carbide surfaces

Several issues related to SiC surfaces are studied in the thesis using scanning tunneling microscopy/spectroscopy (STM/S) and atomic force microscopy (AFM). Specific surfaces examined include electropolished SiC, epitaxial graphene on SiC, and vicinal (i.e. slightly miscut from a low-index direction) SiC that have been subjected to high temperature hydrogen-etching.;The electropolished surfaces are meant to mimic electrochemically etched SiC, which forms a porous network. The chemical treatment of the surface is similar between electropolishing and electrochemical etching, but the etching conditions are slightly different such that the former produces a flat surface (that is amenable to STM study) whereas the latter produces a complex 3-dimensional porous network. We have used these porous SiC layers as semi-permeable membranes in a biosensor, and we find that the material is quite biocompatible. The purpose of the STM/STS study is to investigate the surface properties of the SiC on the atomic scale in an effort to explain this biocompatibility. The observed tunneling spectra are found to be very asymmetric, with a usual amount of current at positive voltages but no observable current at negative voltages. We propose that this behavior is due to surface charge accumulating on an incompletely passivated surface. Measurements on SiC surfaces prepared by various amounts of hydrogen-etching are used to support this interpretation. Comparison with tunneling computations reveals a density of about 10 13 cm-2 fixed charges on both the electro-polished and the H-etched surfaces. The relatively insulating nature observed on the electro-polished SiC surface may provide an explanation for the biocompatibility of the surface.;Graphene, a monolayer of carbon, is a new material for electronic devices. Epitaxial graphene on SiC is fabricated by the Si sublimation method in which a substrate is heated up to about 1350°C in ultra-high vacuum (UHV). The formation of the graphene is monitored using low-energy electron diffraction (LEED) and Auger electron spectroscopy, and the morphology of the graphitized surface is studied using AFM and STM. Use of H-etched SiC substrates enables a relatively flat surface morphology, although residual steps remain due to unintentional miscut of the wafers. Additionally, some surface roughness in the form of small pits is observed, possibly due to the fact that the surface treatments (H-etching and UHV annealing) having been performed in separate vacuum chambers with an intervening transfer through air. Field-effect transistors have been fabricated with our graphene layers; they show a relatively strong held effect at room temperature, with an electron mobility of 535 cm 2/Vs. This value is somewhat lower than that believed to be theoretically possible for this material, and one possible reason may be the nonideal morphology of the surface (i.e. because of the observed steps and pits). Tunneling spectra of the graphene reveal semi-metallic behavior, consistent with that theoretically expected for an isolated layer of graphene. However, additional discrete states are observed in the spectra, possibly arising from bonding at the graphene/SiC interface. The observation of these states provides important input towards an eventual determination of the complete interface structure, and additionally, such states may be relevant in determining the electron mobility of the graphene.;Stepped vicinal SIC{0001} substrates are useful templates for epitaxial growth of various types of layers: thick layers of compound semiconductor (in which the steps help preserving the stacking arrangement in the overlayer), monolayers of graphene, or submonolayer semiconductor layers that form quantum wires along the step edges. Step array produced by H-etching of vicinal SiC (0001) and (0001¯) with various miscut angles have been studied by AFM. H-etching is found to produce full unit-cell-high steps on the (0001) Si-face surfaces, but half unit-cell-high steps on the (0001¯) C-face surfaces. These observations are consistent with an asymmetry in the surface energy (i.e. etch rate) of the two types of step terminations occurring on the different surfaces. For high miscut angles, facet formation is observed on the vicinal Si-face, but less so on the C-face. This difference is interpreted in terms of a lower surface energy of the C-face. In terms of applying the stepped surfaces as a template, a much better uniformity in the step-step separation is found for the C-face surfaces.