Active clamping circuit techniques for area-efficient integrated power transistors switching inductive loads

Solenoids and motors are high-power inductive actuators that are needed for mechanical motion in numerous power electronic applications such as anti-lock brakes, hard-disk drives, printers, and robotics. The trend of integrating power transistors that control high currents through these types of inductive loads is attractive for reducing overall system costs. Additionally, it has become common to include the clamping function that protects the device against inductive kick-back within the integrated circuit such that external clamping power diodes are no longer necessary. This thesis reviews the process of designing an integrated high-power inductive switching circuit and analyzes the effects clamping voltage has on peak junction temperature during the inductor turn-off phase and the resulting reliability performance of the power transistor. Two new active clamping circuits are introduced that are focused on reducing the overall die area of the clamp and the power transistor itself. The first circuit utilizes a Vbe multiplier to reduce the clamping voltage temperature variation and a method to compensate for base current errors is introduced to enable its use on processes with poor NPN beta performance. This circuit consumes 50% less area than a traditional clamp consisting of a Zener diode stack with comparable temperature compensation achieved from multiple forward biased junctions. The second circuit presents a clamp that dynamically adjusts its clamping voltage based on the supply voltage to achieve reduced average power profiles during inductive kick-back in applications, such as automotive electronics, that have high supply over-voltage fault conditions up to 40V. Such a circuit can dramatically reduce the required power transistor area in applications where repetitive energy stress reliability requirements become the dominant sizing factor over Rdson specifications.;Both proposed active clamping circuits have been fabricated in an 180nm high-voltage BiCMOS process along with integrated power transistor devices. Test results of the Vbe multiplier circuit are given over a -40°C to 160°C temperature range and show a negative temperature coefficient is achieved. Repetitive pulse stress tests have been performed on the adaptive clamping circuit that show exponential improvement in reliability performance as the clamping voltage is reduced for a given inductive load switching condition. Cumulative testing is performed that shows the device wear-out can be reduced by operating at a lower clamping voltage the majority of the lifetime of the device. This is important because the power transistor size can be significantly reduced in most cases due to the improved reliability performance.