| Hitherto, in the design of microprocessors, a major barrier to greater single-thread performance has been the inevitable limitation of a single microarchitectural solution being used to execute all types of applications. However, with technology feature-sizes shrinking to the point that it is now possible to package multiple processing cores in a single microprocessor, an opening to this barrier is becoming visible. Although this increase in the number of cores has primarily been viewed as a means to provide thread-level and task-level parallelism, it also provides the opportunity to improve single-thread performance through the incorporation of diversely microarchitected processing cores.;What is more, the aggregate die area taken up by the cores in multicore microprocessors, or Chip Multiprocessors (CMPs), is shrinking in proportion to that of the non-core portion. What this essentially means is that it is becoming cheaper to stamp-out more cores into the design of a CMP -- as long as the cores need not be fully interconnected. Thus, a promising design approach, that forms the central proposal of this thesis, is to incorporate more than one core at each port to the interconnect, gear the microarchitectural design of these cores to distinct workload characteristics, and provide the ability to dynamically select which core to actively employ at each port depending on the immediate application. This solution, which will be referred to as core-selectability, retains the design symmetry that is essential to scalable multithreaded performance (but lost when unique core designs are spread out across the system), while providing the microarchitectural diversity that is essential to single-thread and multiprogrammed performance.;With this approach, the more customized the different core designs are to the behavior of their constituent workload behavior, the more potential there is for performance gain. Thus, accurately studying the potential of this design solution requires accurate understanding of (a) how the microarchitectural design space should be explored, (b) how the workload space should be split up between different core designs, (c) how circuit-level propagation delays should be modeled and accounted for, (d) how overall system performance should be evaluated, and (e) how variability in application phase behavior can be dealt with. These are the issues that are addressed in this thesis.;Among other results, it is revealed that in splitting up the workload space between different core designs, doing so based on the Euclidian distance of applications in their raw workload behavior can lead to suboptimal design choices. It is shown that, in the evaluation of the overall performance of CMP designs, accounting for task arrival behavior can be critical to accuracy. It is shown that core-selectability has the potential to provide notable overall performance benefit to both multi-programmed workloads with different task arrival patterns and multi-threaded workloads. Moreover, it is shown that by extending core-selectability to exploit fine-grain changes in application behavior, with a technique called architectural contesting, it is possible to achieve even greater single-thread performance enhancement. |
