Symbolic sensitivity analysis techniques and applications in analog circuit synthesis

With increasing complexity of integrated circuits and decreasing time-to-market constraints, there was remarkable success in automation of the digital circuit design, but it exposes the lack of comparable analog design automation tools. Although analog components typically constitute only a small portion of the integrated circuits and emerging systems-on-chip (SoC) designs, they are indispensable in all electronic applications that interface with the outside world. Due to the complexity of analog and radio-frequency (RF) circuits, analog circuit design time dominates and becomes a bottleneck in ICs.; There is a growing need for analog design automation tools. One of the main challenges in analog design is sizing. Given an analog topology and a set of high-level design specifications, the size of all components in the circuit must be appropriately determined in order to meet all design target specifications. There are many ways to approach the sizing problem, from manual design and knowledge-based strategies to global optimization engines utilizing a detailed circuit simulator like SPICE.; Typically, most commercial approaches use simulation-in-loop to tackle analog sizing problem due to the high accuracy desired from the estimation process which introduce commercial simulators, like SPICE, to numerically estimate circuit performance and identify critical parameters. Choosing appropriate parameter for sizing in each loop is very critical during the whole sizing process. Sensitivity of an analog circuit is the mathematical measure of variations in the performance metrics due to infinitesimally small perturbations of circuit parameter values which can determine the critical design variables in analog circuit synthesis and can be used repetitively to identify critical parasitics that severely hamper the circuit performance.; In this dissertation, we focus on the development of accurate and efficient symbolic sensitivity analysis for use in the synthesis of analog circuits. We build the sensitivity analysis model and propose the methodologies for performance sensitivity calculations with respect to transistors, capacitors and MOSFETs. We apply different sensitivity analysis techniques to improve the efficiency and accuracy of analog circuit synthesis. In our approach, the parameters chosen for sizing are determined by their sensitivities instead of randomly choosing the parameters to be perturbed. This reduces the iteration time and hence the overall synthesis time considerably. We also build the parasitic estimation model and optimize the parasitics by applying symbolic sensitivity techniques.