Study And Application Of Laser Accurate Localization Techniques In Failure Analysis Of Integrated Circuits

In modern Integrated Circuits(IC)technology,a chip is manufactured through a series of processes.Each of the processed may cause a kind of defect.In the wafer testing and package testing stage of the chip,analyzing the failed chip,locating the failure spot and detecting the physical reason make great contributions to the yield rate of the IC manufacturing.With the improvement of integration,the scaling down of the device and the increase of the metallic interconnect layer,it becomes more and more difficult to precisely locate the failure spot of hard and soft defects in IC.Therefore,accurate and efficient localization technology is also a key in IC failure analysis(FA).This thesis introduces the development of FA technology and several common defect localization technologies.Then it concretely describes the Thermal Laser Stimulation(TLS)technology.A comprehensive model,which depicts the TLS technology better,is proposed on the basis of the previous studies.Based on the research results,a Laser Scanning and Testing System(LSTS)is established and used to test the failure samples together with other facilities,such as Focus Ions Beam(FIB)and Emission Microscope(EMMI).The failure samples contain Microcontroller Unit(MCU),Hex Invertor and multiplexer.The specific research results and conclusions are as follows:(1)A comprehensive Model of TLS technology is put forward,which includes three techniques,Optical Beam Induced Resistance Change(OBIRCH),Thermally Induced Voltage Alteration(TIVA)and Seebeck Effect Imaging(SEI).It gives the relationship between the test parameters and the adjustable parameters in metallic interconnect defect and transistor defect.(2)Based on the Comprehensive Model,a Laser Scanning and Testing System is established with a resolution no more than 0.5 ?m.It can be used to locate the defects of metallic interconnect holes,bridging damage,gate oxygen layer breakdown,highresistance area,leakage current path,et al in semiconductor devices and ICs.The LSTS is sensitive to impedance failure types.Next,the structure and main parameters of LSTS are introduced in detail,and the theoretical expected results of the comprehensive model are verified by experiments.(3)Failure analysis is carried out for the fail samples,MCU CKS32 F,Hex Invertor AC04 and multiplexer ISL71840.Abnormal current variations are detected during the scanning of the first two samples,with the value 20% more than the normal variation value.Therefore,the locations of the generation of abnormal current variations can be regarded as abnormal spots.By using FIB cross section analysis and schematic study,the defects are respectively found in the two samples,which verify that TLS technology is sensitive to these defect types.Abnormal large current pulse was observed in the failed multiplexer sample,and it was conjectured that the latch-up current is generated by thermal-laser.The latch-up current is instable.In the fixed-point irradiation experiment,by adjusting the laser power,the latch-up currents that are respectively stable and instable were observed successively.According to the characteristic that the latch-up holding current and trigger current decrease with the increase of temperature,the previous analysis conjecture was verified.This research constructs the comprehensive model of TLS technology,which provides a detailed theoretical guidance to the failure isolation experiment.A Laser Scanning and Testing System is preliminarily established,which is totally controlled.In addition,the relationships between several physical causes and failure modes of integrated circuits are analyzed,which provides some references for the improvement of chip production and the development of failure analysis in China.