Design Of Readout Circuit For Focal Plane Array Of Laser Three-dimensional Imaging

Laser 3D imaging is a kind of practical photoelectric detection technology,which belongs to active imaging and realizes 3D imaging through signal processing at the back end.In recent years,laser 3D imaging technology has been widely used in intelligent driving,3D face recognition,augmented reality and other emerging technologies,and also has a broad application prospect in the military field.The basic principle of laser 3D imaging technology is to collect the reflected radiation from the detection scene by irradiating the laser pulse to complete the 3D imaging of the target,so as to achieve the detection purpose.A snapshot focal plane array readout circuit based on linear mode APD(Avalanche Photo Diode)device is designed in this paper.Focal plane array readout circuit was based on 0.18?m CMOS(Complementary Metal Oxide Semiconductor)technology,pixel center distance was150?m,array size was 32×32,and the main technical indicators were as follows: The frame rate is 500 Hz,the time digital signal bit is 16 bits,the accuracy is 0.5ns,and the intensity digital signal bit is 12 bits.The time signal and intensity signal of the focal plane array readout circuit are both digital output,which improves the anti-jamming ability.In this paper,the digital signal,strength signal readout to make the simulation design and analysis,including each module simulation,the overall simulation,analysis of error sources,and put forward the error correction scheme.The layout takes into account the limitation of pixel center spacing and the interference of high-frequency signals to highprecision analog signals.The main work of this paper is as follows:1.The overall design scheme of laser three-position imaging is analyzed,various time discrimination schemes are analyzed and compared in detail,and a time discrimination scheme based on time amplitude conversion suitable for the requirements of the indicators in this paper is proposed.2.The overall structure of the focal plane array readout circuit is designed,the main modules are analyzed,and the overall circuit is simulated.The overall circuit has good repeatability,consistency and linearity,with a time accuracy of 0.5ns,a frame frequency of 500 Hz,and a time signal and an intensity signal of 16 bits and 12 bits respectively.3.The error analysis and elimination scheme is proposed,and the correction structure is designed and analyzed and simulated.The results show that the proposed correction scheme can correct the error.The innovation points of this paper are as follows:1.In order to realize simultaneous reading of time signal and strength signal,a circuit structure combining pixel-level time digital signal processing and column-level strength digital signal processing is designed to improve the accuracy of output frame rate and time signal.2.In order to solve the problem of pixel layout size limitation and high precision time signal transmission,a digital signal transmission system suitable for high precision and low power consumption is designed,and the analysis and layout design are made.The invention has been proven to have a smaller layout area and lower power consumption.